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authorKinsey Moore <kmoore@digium.com>2010-07-29 21:51:54 +0000
committerKinsey Moore <kmoore@digium.com>2010-07-29 21:51:54 +0000
commita79307f56d50f5138a067e67e4057bf54c545657 (patch)
tree7e2ecc4aca20b865235c48444c20327030c4d10e /drivers/dahdi/wct4xxp
parentf478ae61c30e56e18f6be218827e1ffeb783f3f6 (diff)
wct4xxp, wcte12xp: restrict signaling and line combinations to what actually works
git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@9056 a0bf4364-ded3-4de4-8d8a-66a801d63aff
Diffstat (limited to 'drivers/dahdi/wct4xxp')
-rw-r--r--drivers/dahdi/wct4xxp/base.c52
1 files changed, 48 insertions, 4 deletions
diff --git a/drivers/dahdi/wct4xxp/base.c b/drivers/dahdi/wct4xxp/base.c
index e902cde..4415270 100644
--- a/drivers/dahdi/wct4xxp/base.c
+++ b/drivers/dahdi/wct4xxp/base.c
@@ -1827,6 +1827,43 @@ static int t4_shutdown(struct dahdi_span *span)
return 0;
}
+static void t4_chan_set_sigcap(struct dahdi_span *span, int x)
+{
+ struct t4_span *wc = container_of(span, struct t4_span, span);
+ struct dahdi_chan *chan = wc->chans[x];
+ chan->sigcap = DAHDI_SIG_CLEAR;
+ /* E&M variant supported depends on span type */
+ if (wc->spantype == TYPE_E1) {
+ /* E1 sigcap setup */
+ if (span->lineconfig & DAHDI_CONFIG_CCS) {
+ /* CCS setup */
+ chan->sigcap |= DAHDI_SIG_MTP2 | DAHDI_SIG_SF |
+ DAHDI_SIG_HARDHDLC;
+ return;
+ }
+ /* clear out sig and sigcap for channel 16 on E1 CAS
+ * lines, otherwise, set it correctly */
+ if (x == 15) {
+ /* CAS signaling channel setup */
+ wc->chans[15]->sigcap = 0;
+ wc->chans[15]->sig = 0;
+ return;
+ }
+ /* normal CAS setup */
+ chan->sigcap |= DAHDI_SIG_EM_E1 | DAHDI_SIG_FXSLS |
+ DAHDI_SIG_FXSGS | DAHDI_SIG_FXSKS | DAHDI_SIG_SF |
+ DAHDI_SIG_FXOLS | DAHDI_SIG_FXOGS | DAHDI_SIG_FXOKS |
+ DAHDI_SIG_CAS | DAHDI_SIG_DACS_RBS;
+ } else {
+ /* T1 sigcap setup */
+ chan->sigcap |= DAHDI_SIG_EM | DAHDI_SIG_FXSLS |
+ DAHDI_SIG_FXSGS | DAHDI_SIG_FXSKS | DAHDI_SIG_MTP2 |
+ DAHDI_SIG_SF | DAHDI_SIG_FXOLS | DAHDI_SIG_FXOGS |
+ DAHDI_SIG_FXOKS | DAHDI_SIG_CAS | DAHDI_SIG_DACS_RBS |
+ DAHDI_SIG_HARDHDLC;
+ }
+}
+
static int t4_spanconfig(struct dahdi_span *span, struct dahdi_lineconfig *lc)
{
int i;
@@ -1863,6 +1900,10 @@ static int t4_spanconfig(struct dahdi_span *span, struct dahdi_lineconfig *lc)
* iterations */
clear_bit(T4_STOP_DMA, &wc->checkflag);
+ /* make sure that sigcaps gets updated if necessary */
+ for (i = 0; i < span->channels; i++)
+ t4_chan_set_sigcap(span, i);
+
/* If we're already running, then go ahead and apply the changes */
if (span->flags & DAHDI_FLAG_RUNNING)
return t4_startup(span);
@@ -2064,11 +2105,15 @@ static void init_spans(struct t4 *wc)
if (ts->spantype == TYPE_T1 || ts->spantype == TYPE_J1) {
ts->span.channels = 24;
ts->span.deflaw = DAHDI_LAW_MULAW;
- ts->span.linecompat = DAHDI_CONFIG_AMI | DAHDI_CONFIG_B8ZS | DAHDI_CONFIG_D4 | DAHDI_CONFIG_ESF;
+ ts->span.linecompat = DAHDI_CONFIG_AMI |
+ DAHDI_CONFIG_B8ZS | DAHDI_CONFIG_D4 |
+ DAHDI_CONFIG_ESF;
} else {
ts->span.channels = 31;
ts->span.deflaw = DAHDI_LAW_ALAW;
- ts->span.linecompat = DAHDI_CONFIG_HDB3 | DAHDI_CONFIG_CCS | DAHDI_CONFIG_CRC4;
+ ts->span.linecompat = DAHDI_CONFIG_AMI |
+ DAHDI_CONFIG_HDB3 | DAHDI_CONFIG_CCS |
+ DAHDI_CONFIG_CRC4;
}
ts->span.chans = ts->chans;
ts->span.flags = DAHDI_FLAG_RBS;
@@ -2088,8 +2133,7 @@ static void init_spans(struct t4 *wc)
for (y=0;y<wc->tspans[x]->span.channels;y++) {
struct dahdi_chan *mychans = ts->chans[y];
sprintf(mychans->name, "TE%d/%d/%d/%d", wc->numspans, wc->num, x + 1, y + 1);
- mychans->sigcap = DAHDI_SIG_EM | DAHDI_SIG_CLEAR | DAHDI_SIG_FXSLS | DAHDI_SIG_FXSGS | DAHDI_SIG_FXSKS | DAHDI_SIG_HARDHDLC | DAHDI_SIG_MTP2 |
- DAHDI_SIG_FXOLS | DAHDI_SIG_FXOGS | DAHDI_SIG_FXOKS | DAHDI_SIG_CAS | DAHDI_SIG_EM_E1 | DAHDI_SIG_DACS_RBS;
+ t4_chan_set_sigcap(&ts->span, x);
mychans->pvt = wc;
mychans->chanpos = y + 1;
}