Fix display of indirect registers and streamline their setting.

* This commit fixes display of indirect registers through the chipregs
  (formly "slics") procfs file. Only the low byte was displayed.
* It also deprecates previous {RW}S in favour of {RW}I. The prevois
  style is still allowed but deprecated, and thus previous scripts will
  still work.



git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@4980 a0bf4364-ded3-4de4-8d8a-66a801d63aff

4 files changed, 159 insertions, 149 deletions

diff --git a/drivers/dahdi/xpp/card_global.c b/drivers/dahdi/xpp/card_global.c
index e4c83f6..d912257 100644
--- a/drivers/dahdi/xpp/card_global.c
+++ b/drivers/dahdi/xpp/card_global.c
@@ -46,6 +46,8 @@ static int proc_xpd_register_read(char *page, char **start, off_t off, int count
 	unsigned long		flags;
 	xpd_t			*xpd = data;
 	reg_cmd_t		*info;
+	bool			do_datah;
+	char			datah_str[50];
 
 	if(!xpd)
 		return -ENODEV;
@@ -54,16 +56,26 @@ static int proc_xpd_register_read(char *page, char **start, off_t off, int count
 	len += sprintf(page + len, "# Writing bad data into this file may damage your hardware!\n");
 	len += sprintf(page + len, "# Consult firmware docs first\n");
 	len += sprintf(page + len, "#\n");
+	do_datah = REG_FIELD(info, do_datah) ? 1 : 0;
+	if(do_datah) {
+		snprintf(datah_str, ARRAY_SIZE(datah_str), "\t%02X",
+			REG_FIELD(info, data_high));
+	} else
+		datah_str[0] = '\0';
 	if(REG_FIELD(info, do_subreg)) {
-		len += sprintf(page + len, "#CH\tOP\tReg.\tSub\tDL\n");
-		len += sprintf(page + len, "%2d\tRS\t%02X\t%02X\t%02X\n",
+		len += sprintf(page + len, "#CH\tOP\tReg.\tSub\tDL%s\n",
+				(do_datah) ? "\tDH" : "");
+		len += sprintf(page + len, "%2d\tRS\t%02X\t%02X\t%02X%s\n",
 				info->portnum,
-				REG_FIELD(info, regnum), REG_FIELD(info, subreg), REG_FIELD(info, data_low));
+				REG_FIELD(info, regnum), REG_FIELD(info, subreg),
+				REG_FIELD(info, data_low), datah_str);
 	} else {
-		len += sprintf(page + len, "#CH\tOP\tReg.\tDL\n");
-		len += sprintf(page + len, "%2d\tRD\t%02X\t%02X\n",
+		len += sprintf(page + len, "#CH\tOP\tReg.\tDL%s\n",
+				(do_datah) ? "\tDH" : "");
+		len += sprintf(page + len, "%2d\tRD\t%02X\t%02X%s\n",
 				info->portnum,
-				REG_FIELD(info, regnum), REG_FIELD(info, data_low));
+				REG_FIELD(info, regnum),
+				REG_FIELD(info, data_low), datah_str);
 	}
 	spin_unlock_irqrestore(&xpd->lock, flags);
 	if (len <= off+count)
@@ -96,7 +108,7 @@ static int execute_chip_command(xpd_t *xpd, const int argc, char *argv[])
 	bool			writing;
 	int			op;		/* [W]rite, [R]ead */
 	int			addr_mode;	/* [D]irect, [I]ndirect, [Mm]ulti */
-	bool			do_indirect = 0;
+	bool			do_subreg = 0;
 	int			regnum;
 	int			subreg;
 	int			data_low;
@@ -148,12 +160,15 @@ static int execute_chip_command(xpd_t *xpd, const int argc, char *argv[])
 	addr_mode = argv[argno][1];
 	switch(addr_mode) {
 		case 'I':
-			do_indirect = 1;
+			XPD_NOTICE(xpd, "'I' is deprecated in register commands. Use 'S' instead.\n");
+			/* fall through */
+		case 'S':
+			do_subreg = 1;
 			num_args += 2;	/* register + subreg */
-			//XPD_DBG(REGS, xpd, "INDIRECT\n");
+			//XPD_DBG(REGS, xpd, "SUBREG\n");
 			break;
 		case 'D':
-			do_indirect = 0;
+			do_subreg = 0;
 			num_args++;	/* register */
 			//XPD_DBG(REGS, xpd, "DIRECT\n");
 			break;
@@ -206,7 +221,7 @@ static int execute_chip_command(xpd_t *xpd, const int argc, char *argv[])
 	}
 	//XPD_DBG(REGS, xpd, "Register is %X\n", regnum);
 	argno++;
-	if(do_indirect) {
+	if(do_subreg) {
 		if(argno >= argc) {
 			XPD_ERR(xpd, "Missing subregister number\n");
 			goto out;
@@ -261,14 +276,14 @@ static int execute_chip_command(xpd_t *xpd, const int argc, char *argv[])
 			portno,		/* portno	*/
 			writing,	/* writing	*/
 			regnum,
-			do_indirect,	/* use subreg	*/
+			do_subreg,	/* use subreg	*/
 			subreg, 	/* subreg	*/
 			data_low,
 			do_datah,	/* use data_high*/
 			data_high);
 #endif
 	ret = xpp_register_request(xpd->xbus, xpd, portno,
-		writing, regnum, do_indirect, subreg,
+		writing, regnum, do_subreg, subreg,
 		data_low, do_datah, data_high, 1);
 out:
 	return ret;
diff --git a/drivers/dahdi/xpp/init_card_1_30 b/drivers/dahdi/xpp/init_card_1_30
index 4075715..e1bbc1f 100755
--- a/drivers/dahdi/xpp/init_card_1_30
+++ b/drivers/dahdi/xpp/init_card_1_30
@@ -29,12 +29,12 @@ use strict;
 #	   accept settings for ALL SLICS).
 #	2. Command word:
 #		- RD	Read Direct register.
-#		- RI	Read Indirect register.
+#		- RS	Read Sub-register.
 #		- WD	Write Direct register.
-#		- WI	Write Indirect register.
+#		- WS	Write Sub-register.
 #	3. Register number in hexadecimal.
-#	4. Low data byte in hexadecimal. (for WD and WI commands).
-#	5. High data byte in hexadecimal. (for WI command only).
+#	4. Low data byte in hexadecimal. (for WD and WS commands).
+#	5. High data byte in hexadecimal. (for WS command only).
 #
 #
 
@@ -147,7 +147,7 @@ sub read_reg($$$) {
 	close(SLICS);
 	die("Failed reading from '$chipregs' ($read_slic,$read_reg,$direct)")
 		unless @reply;
-	if ($direct eq 'I') {
+	if ($direct eq 'S') {
 		return @reply;
 	} else {
 		return $reply[0];
@@ -164,7 +164,7 @@ sub write_reg{#($$$$$) {
 	
 	my $str  = sprintf "%s W%s %02X %02X", 
 		$read_slic, $direct, $read_reg, $reg_val_low;
-	if ($direct eq 'I') {
+	if ($direct eq 'S') {
 		$str .= sprintf " %02X", $reg_val_hi;
 	}
 	write_to_slic_file($str);
@@ -182,72 +182,72 @@ sub log_calib_params() {
 
 sub init_indirect_registers() {
 	return write_to_slic_file("#
-*	WI	1E	00	C2	55
-*	WI	1E	01	E6	51
-*	WI	1E	02	85	4B
-*	WI	1E	03	37	49
+*	WS	1E	00	C2	55
+*	WS	1E	01	E6	51
+*	WS	1E	02	85	4B
+*	WS	1E	03	37	49
                           
-*	WI	1E	04	33	33
-*	WI	1E	05	02	02
-*	WI	1E	06	02	02
-*	WI	1E	07	98	01
+*	WS	1E	04	33	33
+*	WS	1E	05	02	02
+*	WS	1E	06	02	02
+*	WS	1E	07	98	01
                           
-*	WI	1E	08	98	01
-*	WI	1E	09	11	06
-*	WI	1E	0A	02	02
-*	WI	1E	0B	E5	00
+*	WS	1E	08	98	01
+*	WS	1E	09	11	06
+*	WS	1E	0A	02	02
+*	WS	1E	0B	E5	00
                           
-*	WI	1E	0C	1C	0A
-*	WI	1E	0D	30	7B
-*	WI	1E	0E	63	00
-*	WI	1E	0F	00	00
+*	WS	1E	0C	1C	0A
+*	WS	1E	0D	30	7B
+*	WS	1E	0E	63	00
+*	WS	1E	0F	00	00
                           
-*	WI	1E	10	70	78
-*	WI	1E	11	7D	00
-*	WI	1E	12	00	00
-*	WI	1E	13	00	00
+*	WS	1E	10	70	78
+*	WS	1E	11	7D	00
+*	WS	1E	12	00	00
+*	WS	1E	13	00	00
                           
-*	WI	1E	14	F0	7E
-*	WI	1E	15	C0	01
-*	WI	1E	16	00	00
-*	WI	1E	17	00	20
+*	WS	1E	14	F0	7E
+*	WS	1E	15	C0	01
+*	WS	1E	16	00	00
+*	WS	1E	17	00	20
                           
-*	WI	1E	18	00	20
-*	WI	1E	19	00	00
-*	WI	1E	1A	00	20
-*	WI	1E	1B	00	40
+*	WS	1E	18	00	20
+*	WS	1E	19	00	00
+*	WS	1E	1A	00	20
+*	WS	1E	1B	00	40
                           
-*	WI	1E	1C	00	10
-*	WI	1E	1D	00	36
-*	WI	1E	1E	00	10
-*	WI	1E	1F	00	02
+*	WS	1E	1C	00	10
+*	WS	1E	1D	00	36
+*	WS	1E	1E	00	10
+*	WS	1E	1F	00	02
                           
-*	WI	1E	20	C0	07
-*	WI	1E	21	00	26
-*	WI	1E	22	F4	0F
-*	WI	1E	23	00	80
-
-#*	WI	1E	24	20	03
-#*	WI	1E	25	8C	08
-#*	WI	1E	26	00	01
-#*	WI	1E	27	10	00
+*	WS	1E	20	C0	07
+*	WS	1E	21	00	26
+*	WS	1E	22	F4	0F
+*	WS	1E	23	00	80
+
+#*	WS	1E	24	20	03
+#*	WS	1E	25	8C	08
+#*	WS	1E	26	00	01
+#*	WS	1E	27	10	00
                           
-*	WI	1E	24	00	08
-*	WI	1E	25	00	08
-*	WI	1E	26	00	08
-*	WI	1E	27	00	08
+*	WS	1E	24	00	08
+*	WS	1E	25	00	08
+*	WS	1E	26	00	08
+*	WS	1E	27	00	08
                           
-*	WI	1E	28	00	0C
-*	WI	1E	29	00	0C
-*	WI	1E	2B	00	01
+*	WS	1E	28	00	0C
+*	WS	1E	29	00	0C
+*	WS	1E	2B	00	01
                           
-*	WI	1E	63	DA	00
-*	WI	1E	64	60	6B
-*	WI	1E	65	74	00
-*	WI	1E	66	C0	79
+*	WS	1E	63	DA	00
+*	WS	1E	64	60	6B
+*	WS	1E	65	74	00
+*	WS	1E	66	C0	79
                           
-*	WI	1E	67	20	11
-*	WI	1E	68	E0	3B	
+*	WS	1E	67	20	11
+*	WS	1E	68	E0	3B	
 #");
 }
 
@@ -266,8 +266,8 @@ sub save_indirect_filter_params() {
 	for my $slic (@SlicNums) {
 		for my $reg (35 .. 39) {
 			$FilterParams[$slic][$reg] = 
-				[read_reg($slic, $reg, 'I')];
-			write_reg($slic, $reg, 'I', 0, 0x80);
+				[read_reg($slic, $reg, 'S')];
+			write_reg($slic, $reg, 'S', 0, 0x80);
 		}
 	}
 	
@@ -276,7 +276,7 @@ sub save_indirect_filter_params() {
 sub restore_indirect_filter_params() {
 	for my $slic (@SlicNums) {
 		for my $reg (35 .. 39) {
-			write_reg($slic, $reg, 'I', 
+			write_reg($slic, $reg, 'S', 
 				@{$FilterParams[$slic][$reg]});
 		}
 	}
@@ -419,35 +419,35 @@ __DATA__
 *	WD	40	00
 
 # Flush out energy accumulators
-*	WI	1E	58	00 00
-*	WI	1E	59	00 00
-*	WI	1E	5A	00 00
-*	WI	1E	5B	00 00
-*	WI	1E	5C	00 00
-*	WI	1E	5D	00 00
-*	WI	1E	5E	00 00
-*	WI	1E	5F	00 00
-*	WI	1E	61	00 00
-*	WI	1E	58	00 00
-*	WI	1E	C1	00 00
-*	WI	1E	C2	00 00
-*	WI	1E	C3	00 00
-*	WI	1E	C4	00 00
-*	WI	1E	C5	00 00
-*	WI	1E	C6	00 00
-*	WI	1E	C7	00 00
-*	WI	1E	C8	00 00
-*	WI	1E	C9	00 00
-*	WI	1E	CA	00 00
-*	WI	1E	CB	00 00
-*	WI	1E	CC	00 00
-*	WI	1E	CD	00 00
-*	WI	1E	CE	00 00
-*	WI	1E	CF	00 00
-*	WI	1E	D0	00 00
-*	WI	1E	D1	00 00
-*	WI	1E	D2	00 00
-*	WI	1E	D3	00 00
+*	WS	1E	58	00 00
+*	WS	1E	59	00 00
+*	WS	1E	5A	00 00
+*	WS	1E	5B	00 00
+*	WS	1E	5C	00 00
+*	WS	1E	5D	00 00
+*	WS	1E	5E	00 00
+*	WS	1E	5F	00 00
+*	WS	1E	61	00 00
+*	WS	1E	58	00 00
+*	WS	1E	C1	00 00
+*	WS	1E	C2	00 00
+*	WS	1E	C3	00 00
+*	WS	1E	C4	00 00
+*	WS	1E	C5	00 00
+*	WS	1E	C6	00 00
+*	WS	1E	C7	00 00
+*	WS	1E	C8	00 00
+*	WS	1E	C9	00 00
+*	WS	1E	CA	00 00
+*	WS	1E	CB	00 00
+*	WS	1E	CC	00 00
+*	WS	1E	CD	00 00
+*	WS	1E	CE	00 00
+*	WS	1E	CF	00 00
+*	WS	1E	D0	00 00
+*	WS	1E	D1	00 00
+*	WS	1E	D2	00 00
+*	WS	1E	D3	00 00
                 
 # Setting of SLICs offsets
 # New card initialization
@@ -497,16 +497,16 @@ __DATA__
 
 *	WD	6C	01
 
-*	WI	1E	23	00 80
-*	WI	1E	24	20 03
-*	WI	1E	25	8C 08
-*	WI	1E	26	00 01
-*	WI	1E	27	10 00
+*	WS	1E	23	00 80
+*	WS	1E	24	20 03
+*	WS	1E	25	8C 08
+*	WS	1E	26	00 01
+*	WS	1E	27	10 00
 
 #------ Metering tone
-*	WI	1E	17	61 15	# Amplitue Ramp-up
-*	WI	1E	18	61 15	# Max Amplitude
-*	WI	1E	19	FB 30	# Frequency
+*	WS	1E	17	61 15	# Amplitue Ramp-up
+*	WS	1E	18	61 15	# Max Amplitude
+*	WS	1E	19	FB 30	# Frequency
 *	WD	2C	00	# Timer dL
 *	WD	2D	03	# Timer dH
 
diff --git a/drivers/dahdi/xpp/init_card_2_30 b/drivers/dahdi/xpp/init_card_2_30
index bda0792..6a62ec8 100755
--- a/drivers/dahdi/xpp/init_card_2_30
+++ b/drivers/dahdi/xpp/init_card_2_30
@@ -29,12 +29,12 @@ use strict;
 #	   accept settings for ALL SLICS).
 #	2. Command word:
 #		- RD	Read Direct register.
-#		- RI	Read Indirect register.
+#		- RS	Read Sub-register.
 #		- WD	Write Direct register.
-#		- WI	Write Indirect register.
+#		- WS	Write Sub-register.
 #	3. Register number in hexadecimal.
-#	4. Low data byte in hexadecimal. (for WD and WI commands).
-#	5. High data byte in hexadecimal. (for WI command only).
+#	4. Low data byte in hexadecimal. (for WD and WS commands).
+#	5. High data byte in hexadecimal. (for WS command only).
 #
 #
 
@@ -264,6 +264,7 @@ sub opermode_to_string($) {
 sub opermode_verify($) {
 	my $input = shift or die;
 	my %verification_table;
+	my %location_lines;
 	my $mismatches = 0;
 
 	open(F, $input) or die "$0: Failed opening '$input': $!\n";
@@ -277,13 +278,14 @@ sub opermode_verify($) {
 			my ($key, $val) = split(/=/, $p, 2);
 			$verification_table{$location}{$key} = $val;
 		}
+		$location_lines{$location} = $.;
 	}
 	close F;
 	# First test: check for missing data in our program
 	foreach my $location (sort keys %verification_table) {
 		my $mode = $opermode_table{$location};
 		if(! defined $mode) {
-			printf STDERR  "Missing from $0: '$location'\n";
+			printf STDERR  "Missing from $0: '$location' at $input:$location_lines{$location}\n";
 			$mismatches++;
 			next;
 		}
@@ -291,7 +293,7 @@ sub opermode_verify($) {
 		my $str1 = opermode_to_string($mode);
 		my $str2 = opermode_to_string($verify_mode);
 		if($str1 ne $str2) {
-			print STDERR  "DIFF: $location:\n";
+			print STDERR  "DIFF: '$location' at $input:$location_lines{$location}\n";
 			printf STDERR  "\t%-20s: %s\n", "program", $str1;
 			printf STDERR  "\t%-20s: %s\n", "verify", $str2;
 			$mismatches++;
diff --git a/drivers/dahdi/xpp/init_card_3_30 b/drivers/dahdi/xpp/init_card_3_30
index 2f94da9..474b44e 100755
--- a/drivers/dahdi/xpp/init_card_3_30
+++ b/drivers/dahdi/xpp/init_card_3_30
@@ -43,12 +43,12 @@ use strict;
 #	1. CHIP select in decimal (ignored, taken from 3 LSB's of subunit number)
 #	2. Command word:
 #		- RD	Read Direct register.
-#		- RI	Read Indirect register.
+#		- RS	Read Sub-register.
 #		- WD	Write Direct register.
-#		- RI	Write Indirect register.
+#		- WS	Write Sub-register.
 #	3. Register number in hexadecimal.
-#	4. Subregister number in hexadecimal. (for RI and WI commands).
-#	5. Data byte in hexadecimal. (for WD and WI commands only).
+#	4. Subregister number in hexadecimal. (for RS and WS commands).
+#	5. Data byte in hexadecimal. (for WD and WS commands only).
 #
 
 package main;
@@ -288,20 +288,20 @@ sub xhfc_ph_command {
 	#main::logit "xhfc_ph_command(portnum=$portnum)";
 	if ("$cmd" eq "HFC_L1_ACTIVATE_TE") {
 		su_sel($portnum);	# Select port
-		BRI::gen "$portnum	WD	30	60";			# A_SU_WR_STA = (M_SU_ACT & 0x03)
-								# (set activation)
+		BRI::gen "$portnum	WD	30	60";		# A_SU_WR_STA = (M_SU_ACT & 0x03)
+									# (set activation)
 	} elsif ("$cmd" eq "HFC_L1_FORCE_DEACTIVATE_TE") {
 		su_sel($portnum);	# Select port
-		BRI::gen "$portnum	WD	30	40";			# A_SU_WR_STA = (M_SU_ACT & 0x02)
-								# (set deactivation)
+		BRI::gen "$portnum	WD	30	40";		# A_SU_WR_STA = (M_SU_ACT & 0x02)
+									# (set deactivation)
 	} elsif ("$cmd" eq "HFC_L1_ACTIVATE_NT") {
 		su_sel($portnum);	# Select port
-		BRI::gen "$portnum	WD	30	E0";			# A_SU_WR_STA = (M_SU_ACT & 0x03) | 0x80
-								# (set activation + NT)
+		BRI::gen "$portnum	WD	30	E0";		# A_SU_WR_STA = (M_SU_ACT & 0x03) | 0x80
+									# (set activation + NT)
 	} elsif ("$cmd" eq "HFC_L1_DEACTIVATE_NT") {
 		su_sel($portnum);	# Select port
-		BRI::gen "$portnum	WD	30	40";			# A_SU_WR_STA = (M_SU_ACT & 0x02)
-								# (set deactivation)
+		BRI::gen "$portnum	WD	30	40";		# A_SU_WR_STA = (M_SU_ACT & 0x02)
+									# (set deactivation)
 	}
 }
 
@@ -349,7 +349,7 @@ sub init_xhfc($) {
 	main::logit "init_xhfc($portnum)";
 	BRI::gen "#--------------------------- init_xhfc";
 	BRI::gen "$portnum	WD	0D	00";	# r_FIFO_MD: 16 fifos,
-					# 64 bytes for TX and RX each (FIFO mode config)
+							# 64 bytes for TX and RX each (FIFO mode config)
 
 	# software reset to enable R_FIFO_MD setting
 	BRI::gen "$portnum	WD	00	08";	# R_CIRM = M_SRES (soft reset)
@@ -358,29 +358,22 @@ sub init_xhfc($) {
 
 	# amplitude
 	BRI::gen "$portnum	WD	46	80";	# R_PWM_MD: (PWM output mode register)
-					#           PWM push to zero only
+							#           PWM push to zero only
 	BRI::gen "$portnum	WD	39	18";	# R_PWM1: (modulator register for PWM1)
-					#          set duty cycle
+							#          set duty cycle
 
 	BRI::gen "$portnum	WD	0C	11";	# R_FIFO_THRES: (FIFO fill lvl control register)
-					#               RX/TX threshold = 16 bytes
+							#               RX/TX threshold = 16 bytes
 
-	#	--> Wait until (R_STATUS & (M_BUSY | M_PCM_INIT))
- 	# M_BUSY status will be checked after fifo selection
-	BRI::gen "$portnum	WD	0F	80";
-	# set PCM !master mode
+	# set PCM bus mode to slave by default
 	BRI::gen "$portnum	WD	14	08";	# R_PCM_MD0 = PCM slave mode, F0IO duration is 2 HFC_PCLK's
+							# (C4IO, F0IO are inputs)
 
-					# (C4IO, F0IO are inputs)
-
-	# set pll adjust
-	#	WD	14	90	# R_PCM_MD0: Index value to select
-					#            the register at address 15
-	#	WD	15	2C	# R_PCM_MD1: V_PLL_ADJ (DPLL adjust speed), C4IO is 16.384MHz(128 time slots) 
-					#            in the last slot of PCM frame
-	BRI::gen "$portnum	WI	14	98	20";	# R_PCM_MD1: V_PLL_ADJ
-						#            (DPLL adjust speed) in the
-						#            last slot of PCM frame
+	BRI::gen "$portnum	WD	14	98";	# R_PCM_MD0: Index value to select
+							#            the register at address 15
+	BRI::gen "$portnum	WD	15	20";	# R_PCM_MD1: V_PLL_ADJ (DPLL adjust speed), 
+							#            in the last slot of PCM frame
+							#            V_PCM_DR, C4IO  is 16.384MHz(128 time slots) 
 
 	BRI::gen "$portnum	WD	4C	03";	# GPIOGPIO function (not PWM) on GPIO0 and GPIO1 pins
 	BRI::gen "$portnum	WD	4A	03";	# Output enable for GPIO0 and GPIO1 pins