diff options
| author | Tzafrir Cohen <tzafrir.cohen@xorcom.com> | 2011-11-29 23:37:33 +0000 |
|---|---|---|
| committer | Tzafrir Cohen <tzafrir.cohen@xorcom.com> | 2011-11-29 23:37:33 +0000 |
| commit | 4b9f62a79ff751696fa55b661f2cbf219d60d606 (patch) | |
| tree | 2efe745a092e9361d3491f98b73390d339b5401b | |
| parent | 9f4ca623fcd6fe50c8a53dcda8ebc6e8705f8f37 (diff) | |
xpp: pri: fix RS1 init in E1 CAS mode
Force some reserved bits to really be 1 in E1 mode (otherwise
terrorists will win).
(Closes issue DAHLIN-264)
Signed-off-by: Oron Peled <oron.peled@xorcom.com>
git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@10346 a0bf4364-ded3-4de4-8d8a-66a801d63aff
| -rw-r--r-- | drivers/dahdi/xpp/card_pri.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/dahdi/xpp/card_pri.c b/drivers/dahdi/xpp/card_pri.c index 84fa7a2..358e3bc 100644 --- a/drivers/dahdi/xpp/card_pri.c +++ b/drivers/dahdi/xpp/card_pri.c @@ -1034,6 +1034,17 @@ static int pri_lineconfig(xpd_t *xpd, int lineconfig) } #endif if(force_cas) { + if(priv->pri_protocol == PRI_PROTO_E1) { + int rs1 = 0x0B; + + /* + * Set correct X1-X3 bits in the E1 CAS MFAS + * They are unused in E1 and should be 1 + */ + XPD_DBG(GENERAL, xpd, "%s: rs1(0x%02X) = 0x%02X\n", + __FUNCTION__, REG_RS1_E, rs1); + write_subunit(xpd, REG_RS1_E, rs1); + } xsp |= REG_XSP_E_CASEN; /* Same as REG_FMR5_T_EIBR for T1 */ } XPD_DBG(GENERAL, xpd, "%s: xsp(0x%02X) = 0x%02X\n", __FUNCTION__, REG_XSP_E, xsp); |