wct4xxp: Gen5 and qfalc3.1 support

wct4xxp: Added IDs to recognize gen5 firmware

wct4xxp: Fixing errata with the qfalc3.1 chip. Sometimes, in T1 mode, when
the yellow alarm signal is being handled manually, the yellow alarm state
can be stuck. We cannot use automatic mode due to custom debouncing logic,
so we force manual mode and hit a bugfix register defined in the errata.

wct4xxp: Differences between the 2.1 and 3.1 qfalc architecture cause 
previously ignored timing slip interrupts to show up. Now we mask those 
interrupts at the hardware level for each span, while that span is in 
loss of signal, or loss of frame alignment mode. Interrupts are unmasked 
after a valid signal is re-established.

wct4xxp: Reworked the timing code so it makes more logical sense. Both the SCLK
and RCLK timing sources are explicitly defined. This allows for a valid RCLK 
DCO source regardless of SCLK's source. This fixes the broken multiplexer 
problem on the 3.1 chip and is backwards compatible with the 2.1 chips.

wct4xxp: Changed the initialization value for Clock Mode Reg 1
 1) We don't use TCLK in the design, the only xmit clock
    to be referenced is SCLK.
 2) We should disable Clock-Switching, as SYNC is also
    not to be used as a timing source.

wct4xxp: Removed a "dmactrl" set that was clobbering the span's timing, forcing
the fpga into recovered timing(RCLK) output on SCLK even if
it was set to provide system timing(MCLK) on SCLK. The
theory is that this problem only presented itself in FALC
v3.1 due to a difference in PLL types between the two versions.

wct4xxp: Fixed blue alarm detection

wct4xxp: qfalc v3.1 now has integrated xmit resistors.  The external resistors 
connected to XL1 and XL2 pins are now replaced with 0ohm resistors.  Now we 
program PC6.TSRE to switch between 2ohms for T1 and 7.5ohms for E1 mode.

wct4xxp: There appears to be an undocumented errata where the qfalc v3.1 with
regards to CAS robbed bit signalling configuration.  For some reason, it checks
the config of the port configuration registers in addition to the ones that
specify where the robbied bit signalling transmit will come from.  For our
case, we want it to come from the transmit register block.  This new port
configuration allows v3.1 to continue to use the register block as expected
instead of from an external serial pin.



git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/branches/2.2@8332 a0bf4364-ded3-4de4-8d8a-66a801d63aff

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