diff options
| author | Tzafrir Cohen <tzafrir.cohen@xorcom.com> | 2010-07-13 07:22:02 +0000 |
|---|---|---|
| committer | Tzafrir Cohen <tzafrir.cohen@xorcom.com> | 2010-07-13 07:22:02 +0000 |
| commit | ae46cd5bf15561cfe70625b4853e45bf8b955d9e (patch) | |
| tree | 05fe4b8e4754cb4215e383d1a66f393c72a79299 /drivers/dahdi/xpp/init_card_4_30 | |
| parent | cbf51d66f2fd97b471e724a29d7587af8b5ecbe4 (diff) | |
partial fix of T1 returning signaling register in non-CAS mode
git-svn-id: http://svn.asterisk.org/svn/dahdi/linux/trunk@8872 a0bf4364-ded3-4de4-8d8a-66a801d63aff
Diffstat (limited to 'drivers/dahdi/xpp/init_card_4_30')
| -rwxr-xr-x | drivers/dahdi/xpp/init_card_4_30 | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/drivers/dahdi/xpp/init_card_4_30 b/drivers/dahdi/xpp/init_card_4_30 index 7eae895..9bf33d1 100755 --- a/drivers/dahdi/xpp/init_card_4_30 +++ b/drivers/dahdi/xpp/init_card_4_30 @@ -238,6 +238,7 @@ sub write_pri_info { sub port_setup($) { my $port = shift; my $portno = $port->{PORT_NUM}; + my $pri_protocol = $port->get_pri_protocol; my $cmr5 = sprintf("%x", ($portno << 5)); @@ -302,10 +303,13 @@ sub port_setup($) { PRI::gen "$portno WD 3F $sic2"; # SIC2: No FFS, no center receive elastic buffer, data active at phase ($sic >> 1) # enable the following interrupt sources + PRI::gen "$portno WD 14 F7"; # IMR0 (Interrupt Mask Register2): Enable CASC_E1/RSC_T1 PRI::gen "$portno WD 16 00"; # IMR2 (Interrupt Mask Register2): Enable ALL PRI::gen "$portno WD 17 3F"; # IMR3 ~ES, ~SEC (Enable ES and SEC interrupts) PRI::gen "$portno WD 18 00"; # IMR4: Enable ALL + PRI::gen "$portno WD 46 80"; # GCR: (Global Configuration Register) + # VIS (Masked Interrupts Visible) PRI::gen "$portno WD 08 04"; # IPC: SYNC is 8 Khz @@ -334,9 +338,14 @@ sub port_setup($) { # MDS (Mode Select) = 100 (No address comparison) # HRAC (Receiver Active - HDLC channel 1) # RFT2 (HDLC Receive FIFO is 64 byte deep) - PRI::gen "$portno WD 09 18"; # CCR1 (Common Configuration Register1) + my $ccr1 = 0x18; # CCR1 (Common Configuration Register1) # EITS (Enable Internal Time Slot 0 to 31 Signalling) # ITF (Interframe Time Fill) + if ( $pri_protocol eq 'T1' ) { + $ccr1 |= 0x80; # RSCC (Serial CAS Format Selection) + } + + PRI::gen "$portno WD 09 %02X", $ccr1; PRI::gen "$portno WD 0A 04"; # CCR2 (Common Configuration Register2) # RCRC (enable CRC - HDLC channel 1enable CRC - HDLC channel 1) PRI::gen "$portno WD 0C 00"; # RTR1 (Receive Time Slot register 1) |