diff options
Diffstat (limited to 'software/octdeviceapi/oct6100api/oct6100_api/oct6100_chip_open.c')
| -rw-r--r-- | software/octdeviceapi/oct6100api/oct6100_api/oct6100_chip_open.c | 702 |
1 files changed, 650 insertions, 52 deletions
diff --git a/software/octdeviceapi/oct6100api/oct6100_api/oct6100_chip_open.c b/software/octdeviceapi/oct6100api/oct6100_api/oct6100_chip_open.c index 54727d2..3f4baed 100644 --- a/software/octdeviceapi/oct6100api/oct6100_api/oct6100_chip_open.c +++ b/software/octdeviceapi/oct6100api/oct6100_api/oct6100_chip_open.c @@ -24,9 +24,9 @@ You should have received a copy of the GNU General Public License along with the OCT6100 GPL API; if not, write to the Free Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. -$Octasic_Release: OCT612xAPI-01.00-PR43 $ +$Octasic_Release: OCT612xAPI-01.00-PR47 $ -$Octasic_Revision: 312 $ +$Octasic_Revision: 336 $ \*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ @@ -241,6 +241,7 @@ UINT32 Oct6100ChipOpenDef( f_pChipOpen->fEnableChannelRecording = FALSE; f_pChipOpen->fEnableProductionBist = FALSE; + f_pChipOpen->ulProductionBistMode = cOCT6100_PRODUCTION_BIST_STANDARD; f_pChipOpen->ulNumProductionBistLoops = 1; return cOCT6100_ERR_OK; @@ -293,7 +294,6 @@ UINT32 Oct6100ChipOpen( /* Save the process context specified by the user. */ f_pApiInstance->pProcessContext = f_pChipOpen->pProcessContext; - /* Create serialization object handles. */ ulResult = Oct6100ApiCreateSerializeObjects( f_pApiInstance, f_pChipOpen->ulUserChipId ); if ( ulResult != cOCT6100_ERR_OK ) @@ -863,10 +863,178 @@ UINT32 Oct6100ApiGetVersion( } #endif +/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\ + +Function: Oct6100ApiGetCapacityPins + +Description: Retrieves the Capcity Pins value. + +------------------------------------------------------------------------------- +| Argument | Description +------------------------------------------------------------------------------- + +f_pGetCapacityPins Pointer to the parameters structure needed + by GetCapacityPins(). + +\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ +#if !SKIP_Oct6100ApiGetCapacityPinsDef +UINT32 Oct6100ApiGetCapacityPinsDef( + tPOCT6100_API_GET_CAPACITY_PINS f_pGetCapacityPins) +{ + + f_pGetCapacityPins->pProcessContext = NULL; + f_pGetCapacityPins->ulUserChipId = 0; + f_pGetCapacityPins->ulMemoryType = cOCT6100_MEM_TYPE_DDR; + f_pGetCapacityPins->ulCapacityValue = cOCT6100_INVALID_VALUE; + f_pGetCapacityPins->fEnableMemClkOut = TRUE; + f_pGetCapacityPins->ulMemClkFreq = 133000000; + + return cOCT6100_ERR_OK; +} +#endif + +#if !SKIP_Oct6100ApiGetCapacityPins +UINT32 Oct6100ApiGetCapacityPins( + tPOCT6100_API_GET_CAPACITY_PINS f_pGetCapacityPins ) +{ + + UINT32 ulResult; + + tOCT6100_INSTANCE_API ApiInstance; + + Oct6100UserMemSet(&ApiInstance,0,sizeof(tOCT6100_INSTANCE_API)); + + /*Check parameters*/ + if ( f_pGetCapacityPins->ulMemClkFreq != cOCT6100_MCLK_FREQ_133_MHZ && + f_pGetCapacityPins->ulMemClkFreq != cOCT6100_MCLK_FREQ_125_MHZ && + f_pGetCapacityPins->ulMemClkFreq != cOCT6100_MCLK_FREQ_117_MHZ && + f_pGetCapacityPins->ulMemClkFreq != cOCT6100_MCLK_FREQ_108_MHZ && + f_pGetCapacityPins->ulMemClkFreq != cOCT6100_MCLK_FREQ_100_MHZ && + f_pGetCapacityPins->ulMemClkFreq != cOCT6100_MCLK_FREQ_92_MHZ && + f_pGetCapacityPins->ulMemClkFreq != cOCT6100_MCLK_FREQ_83_MHZ && + f_pGetCapacityPins->ulMemClkFreq != cOCT6100_MCLK_FREQ_75_MHZ ) + return cOCT6100_ERR_OPEN_MEM_CLK_FREQ; + + if ( f_pGetCapacityPins->fEnableMemClkOut != TRUE && + f_pGetCapacityPins->fEnableMemClkOut != FALSE ) + return cOCT6100_ERR_OPEN_ENABLE_MEM_CLK_OUT; + + if ( f_pGetCapacityPins->ulMemoryType != cOCT6100_MEM_TYPE_SDR && + f_pGetCapacityPins->ulMemoryType != cOCT6100_MEM_TYPE_DDR && + f_pGetCapacityPins->ulMemoryType != cOCT6100_MEM_TYPE_SDR_PLL_BYPASS ) + return cOCT6100_ERR_OPEN_MEMORY_TYPE; + + + + ApiInstance.pProcessContext = f_pGetCapacityPins->pProcessContext; + + + + ulResult = Oct6100ApiReadCapacity(&ApiInstance, f_pGetCapacityPins); + + + + return ulResult; +} +#endif /*************************** PRIVATE FUNCTIONS *****************************/ +/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\ + +Function: Oct6100ApiReadCapacity + +Description: Read the capacity pins using modified functions from the openchip. + +------------------------------------------------------------------------------- +| Argument | Description +------------------------------------------------------------------------------- + +f_pChipOpen Pointer to chip configuration structure. + +\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ +#if !SKIP_OCT6100ApiReadCapacity +UINT32 Oct6100ApiReadCapacity( IN tPOCT6100_INSTANCE_API f_pApiInstance, + IN tPOCT6100_API_GET_CAPACITY_PINS f_pGetCapacityPins) +{ + UINT32 ulResult; + tOCT6100_READ_PARAMS ReadParams; + UINT16 usReadData; + + /*Read capacity Pins*/ + ReadParams.pProcessContext = f_pGetCapacityPins->pProcessContext; + ReadParams.ulUserChipId = f_pGetCapacityPins->ulUserChipId; + ReadParams.pusReadData = &usReadData; + + /*Check the Reset register*/ + ReadParams.ulReadAddress = 0x100; + mOCT6100_DRIVER_READ_API( ReadParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + if ((usReadData & 0xFFFF) != 0x0000) + return cOCT6100_ERR_CAP_PINS_INVALID_CHIP_STATE; + + /* Test the CPU registers. */ + ulResult = Oct6100ApiCpuRegisterBistReadCap( f_pApiInstance, f_pGetCapacityPins ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Boot the FC2 PLL. */ + ulResult = Oct6100ApiBootFc2PllReadCap( f_pApiInstance,f_pGetCapacityPins ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Program the FC1 PLL. */ + ulResult = Oct6100ApiProgramFc1PllReadCap( f_pApiInstance,f_pGetCapacityPins ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + if ( (f_pGetCapacityPins->ulMemoryType == cOCT6100_MEM_TYPE_SDR) || + (f_pGetCapacityPins->ulMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS) ) + { + ReadParams.ulReadAddress = 0x168; + } + else + ReadParams.ulReadAddress = 0x166; + + mOCT6100_DRIVER_READ_API( ReadParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + switch (usReadData & 0xF) + { + case 0x9: + f_pGetCapacityPins->ulCapacityValue = 16; + break; + case 0x8: + f_pGetCapacityPins->ulCapacityValue = 32; + break; + case 0xE: + f_pGetCapacityPins->ulCapacityValue = 64; + break; + case 0x0: + f_pGetCapacityPins->ulCapacityValue = 128; + break; + case 0x2: + f_pGetCapacityPins->ulCapacityValue = 256; + break; + case 0x5: + f_pGetCapacityPins->ulCapacityValue = 512; + break; + case 0x6: + f_pGetCapacityPins->ulCapacityValue = 672; + break; + default: + f_pGetCapacityPins->ulCapacityValue = (usReadData & 0xF); + return cOCT6100_ERR_CAP_PINS_INVALID_CAPACITY_VALUE; + } + + return cOCT6100_ERR_OK; +} +#endif + /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\ Function: Oct6100ApiCheckChipConfiguration @@ -1146,6 +1314,10 @@ UINT32 Oct6100ApiCheckChipConfiguration( { if ( f_pChipOpen->ulNumProductionBistLoops == 0 ) return cOCT6100_ERR_OPEN_NUM_PRODUCTION_BIST_LOOPS; + + if ( (f_pChipOpen->ulProductionBistMode != cOCT6100_PRODUCTION_BIST_STANDARD) && + (f_pChipOpen->ulProductionBistMode != cOCT6100_PRODUCTION_BIST_SHORT) ) + return cOCT6100_ERR_OPEN_PRODUCTION_BIST_MODE; } /* If the production BIST has been requested, make sure all */ @@ -1266,6 +1438,7 @@ UINT32 Oct6100ApiCopyChipConfiguration( pSharedInfo->ChipConfig.fEnableProductionBist = (UINT8)( f_pChipOpen->fEnableProductionBist & 0xFF ); + pSharedInfo->ChipConfig.ulProductionBistMode = f_pChipOpen->ulProductionBistMode; pSharedInfo->ChipConfig.ulNumProductionBistLoops = f_pChipOpen->ulNumProductionBistLoops; return cOCT6100_ERR_OK; @@ -1373,6 +1546,7 @@ UINT32 Oct6100ApiInitializeMiscellaneousVariables( pSharedInfo->ImageInfo.fSoutAppliedGainStat = FALSE; pSharedInfo->ImageInfo.fListenerEnhancement = FALSE; pSharedInfo->ImageInfo.fRoutNoiseReduction = FALSE; + pSharedInfo->ImageInfo.fRoutNoiseReductionLevel = FALSE; pSharedInfo->ImageInfo.fAnrSnrEnhancement = FALSE; pSharedInfo->ImageInfo.fAnrVoiceNoiseSegregation = FALSE; pSharedInfo->ImageInfo.fRinMute = FALSE; @@ -1482,13 +1656,11 @@ UINT32 Oct6100ApiCalculateInstanceSizes( ulResult = Oct6100ApiGetChannelsEchoSwSizes( f_pChipOpen, f_pInstSizes ); if ( ulResult != cOCT6100_ERR_OK ) return ulResult; - /*-----------------------------------------------------------------------------*/ /* Memory needed by the TSI structures. */ ulResult = Oct6100ApiGetTsiCnctSwSizes( f_pChipOpen, f_pInstSizes ); if ( ulResult != cOCT6100_ERR_OK ) return ulResult; - /*-----------------------------------------------------------------------------*/ /* Calculate memory needed for the conference bridges. */ ulResult = Oct6100ApiGetConfBridgeSwSizes( f_pChipOpen, f_pInstSizes ); @@ -1514,7 +1686,6 @@ UINT32 Oct6100ApiCalculateInstanceSizes( ulResult = Oct6100ApiGetPhasingTsstSwSizes( f_pChipOpen, f_pInstSizes ); if ( ulResult != cOCT6100_ERR_OK ) return ulResult; - /*-----------------------------------------------------------------------------*/ /* Calculate memory needed for the ADPCM channels. */ ulResult = Oct6100ApiGetAdpcmChanSwSizes( f_pChipOpen, f_pInstSizes ); @@ -1770,13 +1941,11 @@ UINT32 Oct6100ApiInitializeInstanceMemory( ulResult = Oct6100ApiChannelsEchoSwInit( f_pApiInstance ); if ( ulResult != cOCT6100_ERR_OK ) return ulResult; - /*-----------------------------------------------------------------------------*/ /* Initialize the API TSI connection structures. */ ulResult = Oct6100ApiTsiCnctSwInit( f_pApiInstance ); if ( ulResult != cOCT6100_ERR_OK ) return ulResult; - /*-----------------------------------------------------------------------------*/ /* Initialize the API conference bridges. */ ulResult = Oct6100ApiConfBridgeSwInit( f_pApiInstance ); @@ -1794,7 +1963,6 @@ UINT32 Oct6100ApiInitializeInstanceMemory( ulResult = Oct6100ApiPhasingTsstSwInit( f_pApiInstance ); if ( ulResult != cOCT6100_ERR_OK ) return ulResult; - /*-----------------------------------------------------------------------------*/ /* Initialize the API ADPCM channels. */ ulResult = Oct6100ApiAdpcmChanSwInit( f_pApiInstance ); @@ -2056,7 +2224,241 @@ UINT32 Oct6100ApiDecodeKeyAndBist( } #endif +/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\ + +Function: Oct6100ApiBootFc2PllReadCap + +Description: Configures the chip's FC2 PLL. Special version for GetcapacityPins. + +------------------------------------------------------------------------------- +| Argument | Description +------------------------------------------------------------------------------- +f_pApiInstance Pointer to API instance. This memory is used to keep the + present state of the chip and all its resources. + +\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ +UINT32 Oct6100ApiBootFc2PllReadCap( + IN tPOCT6100_INSTANCE_API f_pApiInstance, + IN tPOCT6100_API_GET_CAPACITY_PINS f_pGetCapacityPins) +{ + tOCT6100_WRITE_PARAMS WriteParams; + UINT32 aulWaitTime[ 2 ]; + UINT32 ulResult; + UINT32 ulFc2PllDivisor = 0; + UINT32 ulMtDivisor = 0; + UINT32 ulFcDivisor = 0; + + /* Set the process context and user chip ID parameters once and for all. */ + WriteParams.pProcessContext = f_pGetCapacityPins->pProcessContext; + + WriteParams.ulUserChipId = f_pGetCapacityPins->ulUserChipId; + + /* First put the chip and main registers in soft-reset. */ + WriteParams.ulWriteAddress = 0x100; + WriteParams.usWriteData = 0x0; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ) + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + ulFc2PllDivisor = 0x1050; + ulMtDivisor = 0x4300; + ulFcDivisor = 0x4043; + + /* Setup delay chains. */ + if ( (f_pGetCapacityPins->ulMemoryType == cOCT6100_MEM_TYPE_SDR) || (f_pGetCapacityPins->ulMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS) ) + { + /* SDRAM */ + WriteParams.ulWriteAddress = 0x1B0; + WriteParams.usWriteData = 0x1003; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x1B2; + WriteParams.usWriteData = 0x0021; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x1B4; + WriteParams.usWriteData = 0x4030; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x1B6; + WriteParams.usWriteData = 0x0021; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + } + else /* if ( cOCT6100_MEM_TYPE_DDR == pChipConfig->byMemoryType ) */ + { + /* DDR */ + WriteParams.ulWriteAddress = 0x1B0; + WriteParams.usWriteData = 0x201F; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x1B2; + WriteParams.usWriteData = 0x0021; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x1B4; + WriteParams.usWriteData = 0x1000; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x1B6; + WriteParams.usWriteData = 0x0021; + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + } + + /* udqs */ + WriteParams.ulWriteAddress = 0x1B8; + WriteParams.usWriteData = 0x1003; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x1BA; + WriteParams.usWriteData = 0x0021; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* ldqs */ + WriteParams.ulWriteAddress = 0x1BC; + WriteParams.usWriteData = 0x1000; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x1BE; + WriteParams.usWriteData = 0x0021; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x12C; + WriteParams.usWriteData = 0x0000; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x12E; + WriteParams.usWriteData = 0x0000; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Select fc2pll for fast_clk and mtsclk sources. Select mem_clk_i for afclk. */ + WriteParams.ulWriteAddress = 0x140; + WriteParams.usWriteData = (UINT16)ulMtDivisor; + + if ( f_pGetCapacityPins->ulMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS ) + WriteParams.usWriteData |= 0x0001; + else + WriteParams.usWriteData |= 0x0004; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x144; + WriteParams.usWriteData = (UINT16)ulFcDivisor; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.ulWriteAddress = 0x13E; + WriteParams.usWriteData = 0x0001; /* Remove reset from above divisors */ + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Select upclk directly as ref source for fc2pll. */ + WriteParams.ulWriteAddress = 0x134; + WriteParams.usWriteData = 0x0001; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Setup fc2pll. */ + WriteParams.ulWriteAddress = 0x132; + WriteParams.usWriteData = (UINT16)ulFc2PllDivisor; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.usWriteData |= 0x02; /* Raise fb divisor reset. */ + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + WriteParams.usWriteData |= 0x80; /* Raise IDDTN signal.*/ + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Wait for fc2pll to stabilize. */ + aulWaitTime[ 0 ] = 2000; + aulWaitTime[ 1 ] = 0; + ulResult = Oct6100ApiWaitForTime( f_pApiInstance, aulWaitTime ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Drive mem_clk_o out on proper interface. */ + if ( TRUE == f_pGetCapacityPins->fEnableMemClkOut ) + { + if ( (f_pGetCapacityPins->ulMemoryType == cOCT6100_MEM_TYPE_SDR) || (f_pGetCapacityPins->ulMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS) ) + { + WriteParams.ulWriteAddress = 0x128; + WriteParams.usWriteData = 0x0301; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + } + + if ( f_pGetCapacityPins->ulMemoryType == cOCT6100_MEM_TYPE_DDR || f_pGetCapacityPins->ulMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS ) + { + WriteParams.ulWriteAddress = 0x12A; + WriteParams.usWriteData = 0x000F; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + } + } + + return cOCT6100_ERR_OK; +} /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\ Function: Oct6100ApiBootFc2Pll @@ -2413,7 +2815,83 @@ UINT32 Oct6100ApiBootFc2Pll( } #endif +/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\ + +Function: Oct6100ApiProgramFc1PllReadCap +Description: Configures the chip's FC1 PLL. Special version for getCapacityPins. + +------------------------------------------------------------------------------- +| Argument | Description +------------------------------------------------------------------------------- +f_pApiInstance Pointer to API instance. This memory is used to keep the + present state of the chip and all its resources. + +\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ +UINT32 Oct6100ApiProgramFc1PllReadCap( + IN tPOCT6100_INSTANCE_API f_pApiInstance, + IN tPOCT6100_API_GET_CAPACITY_PINS f_pGetCapacityPins) +{ + tOCT6100_WRITE_PARAMS WriteParams; + UINT32 aulWaitTime[ 2 ]; + UINT32 ulResult; + + /* Set the process context and user chip ID parameters once and for all. */ + WriteParams.pProcessContext = f_pApiInstance->pProcessContext; + + WriteParams.ulUserChipId = f_pGetCapacityPins->ulUserChipId; + + /* Programm P/Z bits. */ + WriteParams.ulWriteAddress = 0x130; + + if ( f_pGetCapacityPins->ulMemoryType == cOCT6100_MEM_TYPE_SDR_PLL_BYPASS ) + WriteParams.usWriteData = 0x0041; + else + WriteParams.usWriteData = 0x0040; + + WriteParams.usWriteData |= ( f_pGetCapacityPins->ulMemoryType << 8 ); + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Raise FB divisor. */ + WriteParams.usWriteData |= 0x0002; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Raise IDDTN. */ + WriteParams.usWriteData |= 0x0080; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Wait for fc1pll to stabilize. */ + aulWaitTime[ 0 ] = 2000; + aulWaitTime[ 1 ] = 0; + ulResult = Oct6100ApiWaitForTime( f_pApiInstance, aulWaitTime ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Enable all the clock domains to do reset procedure. */ + WriteParams.ulWriteAddress = 0x186; + WriteParams.usWriteData = 0x015F; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + aulWaitTime[ 0 ] = 15000; + aulWaitTime[ 1 ] = 0; + ulResult = Oct6100ApiWaitForTime( f_pApiInstance, aulWaitTime ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + return cOCT6100_ERR_OK; +} /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\ Function: Oct6100ApiProgramFc1Pll @@ -2789,7 +3267,119 @@ UINT32 Oct6100ApiLoadImage( } #endif +/*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\ + +Function: Oct6100ApiCpuRegisterBistReadCap + +Description: Tests the operation of the CPU registers. Special Version for + GetCapacityPins + +------------------------------------------------------------------------------- +| Argument | Description +------------------------------------------------------------------------------- +f_pApiInstance Pointer to API instance. This memory is used to keep the + present state of the chip and all its resources. +\*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/ +UINT32 Oct6100ApiCpuRegisterBistReadCap( + IN tPOCT6100_INSTANCE_API f_pApiInstance, + IN tPOCT6100_API_GET_CAPACITY_PINS f_pGetCapacityPins + ) +{ + tOCT6100_WRITE_PARAMS WriteParams; + tOCT6100_READ_PARAMS ReadParams; + UINT32 ulResult; + UINT16 i; + UINT16 usReadData; + + /* Set the process context and user chip ID parameters once and for all. */ + WriteParams.pProcessContext = f_pApiInstance->pProcessContext; + + WriteParams.ulUserChipId = f_pGetCapacityPins->ulUserChipId; + + ReadParams.pProcessContext = f_pApiInstance->pProcessContext; + + ReadParams.ulUserChipId = f_pGetCapacityPins->ulUserChipId; + + /* Assign read data pointer that will be used throughout the function. */ + ReadParams.pusReadData = &usReadData; + + /* Start with a walking bit test. */ + for ( i = 0; i < 16; i ++ ) + { + /* Write at address 0x150.*/ + WriteParams.ulWriteAddress = 0x150; + WriteParams.usWriteData = (UINT16)( 0x1 << i ); + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Write at address 0x180.*/ + WriteParams.ulWriteAddress = 0x180; + WriteParams.usWriteData = (UINT16)( 0x1 << ( 15 - i ) ); + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Now read back the two registers to make sure the acceses were successfull. */ + ReadParams.ulReadAddress = 0x150; + + mOCT6100_DRIVER_READ_API( ReadParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + if ( usReadData != ( 0x1 << i ) ) + return cOCT6100_ERR_OPEN_CPU_REG_BIST_ERROR; + + ReadParams.ulReadAddress = 0x180; + + mOCT6100_DRIVER_READ_API( ReadParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + if ( usReadData != ( 0x1 << ( 15 - i ) ) ) + return cOCT6100_ERR_OPEN_CPU_REG_BIST_ERROR; + } + + /* Write at address 0x150. */ + WriteParams.ulWriteAddress = 0x150; + WriteParams.usWriteData = 0xCAFE; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Write at address 0x180. */ + WriteParams.ulWriteAddress = 0x180; + WriteParams.usWriteData = 0xDECA; + + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + /* Now read back the two registers to make sure the acceses were successfull. */ + ReadParams.ulReadAddress = 0x150; + + mOCT6100_DRIVER_READ_API( ReadParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + if ( usReadData != 0xCAFE ) + return cOCT6100_ERR_OPEN_CPU_REG_BIST_ERROR; + + ReadParams.ulReadAddress = 0x180; + + mOCT6100_DRIVER_READ_API( ReadParams, ulResult ); + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + if ( usReadData != 0xDECA ) + return cOCT6100_ERR_OPEN_CPU_REG_BIST_ERROR; + + return cOCT6100_ERR_OK; +} /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*\ Function: Oct6100ApiCpuRegisterBist @@ -3810,7 +4400,10 @@ UINT32 Oct6100ApiProgramNLP( { if ( pSharedInfo->ChipConfig.fEnableProductionBist == TRUE ) { - WriteParams.usWriteData = cOCT6100_PRODUCTION_BOOT_TYPE; + if (pSharedInfo->ChipConfig.ulProductionBistMode == cOCT6100_PRODUCTION_BIST_SHORT) + WriteParams.usWriteData = cOCT6100_PRODUCTION_SHORT_BOOT_TYPE; + else + WriteParams.usWriteData = cOCT6100_PRODUCTION_BOOT_TYPE; } else { @@ -3892,7 +4485,8 @@ UINT32 Oct6100ApiProgramNLP( if ( pSharedInfo->ChipConfig.fEnableProductionBist == TRUE ) { /* Should read 0x0007 when bisting. */ - if ( ( usReadHighData & 0xFFFF ) == cOCT6100_PRODUCTION_BOOT_TYPE ) + if ( (( usReadHighData & 0xFFFF ) == cOCT6100_PRODUCTION_BOOT_TYPE) || + (( usReadHighData & 0xFFFF ) == cOCT6100_PRODUCTION_SHORT_BOOT_TYPE) ) { /* Verify if the bist has started successfully. */ if ( ( usReadData & 0xFFFF ) == 0x0002 ) @@ -5269,6 +5863,11 @@ UINT32 Oct6100ApiRandomMemoryWrite( UINT32 ulResult, i, j; UINT32 ulBistAddress; UINT16 usReadData; + UINT32 aulBistAddress[20]={0x00000000, 0x00000002, 0x00000004, 0x007FFFFE, + 0x00900000, 0x00900006, 0x00900008, 0x009FFFFE, + 0x01000000, 0x0100000A, 0x0200000C, 0x01FFFFFE, + 0x03000000, 0x03000002, 0x04000004, 0x03FFFFFE, + 0x04000000, 0x05000006, 0x06000008, 0x07FFFFFE}; /* Get local pointer to shared portion of instance. */ pSharedInfo = f_pApiInstance->pSharedInfo; @@ -5282,51 +5881,54 @@ UINT32 Oct6100ApiRandomMemoryWrite( ReadParams.ulUserChipId = pSharedInfo->ChipConfig.ulUserChipId; - /* Make sure we don't perform more access then the size of our BIST resources. */ - if ( f_ulNumAccesses > 1024 ) - return cOCT6100_ERR_FATAL_C0; - /* Determine mask for number of data bits. */ ulDataMask = (1 << f_ulNumDataBits) - 1; - /* Bist all data pin. */ - for ( i = 0; i < 32; i += 2 ) - { - WriteParams.ulWriteAddress = f_ulMemBase + i * 2; - WriteParams.usWriteData = (UINT16)(0x1 << (i / 2)); - - mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ) - if ( ulResult != cOCT6100_ERR_OK ) - return ulResult; + /* Write specific data to specific address */ + WriteParams.ulWriteAddress = f_ulMemBase | 0x00001000; + WriteParams.usWriteData = 0xCAFE; - WriteParams.ulWriteAddress = f_ulMemBase + i * 2 + 2; - WriteParams.usWriteData = (UINT16)(0x1 << (i / 2)); + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ) + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; + + for(j=0; j<20; j++) + { + /* Change address to test lower and higher part of the 32 bit bus */ + ulBistAddress = aulBistAddress[j]; + ulBistAddress &= f_ulMemSize - 2; + ulBistAddress |= f_ulMemBase; - mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ) - if ( ulResult != cOCT6100_ERR_OK ) - return ulResult; - } + /* Bist 16 data pins of this address */ + for ( i = 0; i < 16; i ++) + { + WriteParams.ulWriteAddress = ulBistAddress; + WriteParams.usWriteData = (UINT16)(0x1 << i); - /* Read back the data written. */ - for ( i = 0; i < 32; i += 2 ) - { - ReadParams.ulReadAddress = f_ulMemBase + i * 2; - ReadParams.pusReadData = &usReadData; - mOCT6100_DRIVER_READ_API( ReadParams, ulResult ) - if ( ulResult != cOCT6100_ERR_OK ) - return ulResult; + mOCT6100_DRIVER_WRITE_API( WriteParams, ulResult ) + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; - if ( usReadData != (UINT16)(0x1 << (i / 2)) ) - return f_ulErrorCode; + /* Read back the specific data to flush the data bus.*/ + ReadParams.ulReadAddress = f_ulMemBase | 0x00001000; + ReadParams.pusReadData = &usReadData; + mOCT6100_DRIVER_READ_API( ReadParams, ulResult ) + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; - ReadParams.ulReadAddress = f_ulMemBase + i * 2 + 2; - ReadParams.pusReadData = &usReadData; - mOCT6100_DRIVER_READ_API( ReadParams, ulResult ) - if ( ulResult != cOCT6100_ERR_OK ) - return ulResult; + if ( usReadData != 0xCAFE ) + return f_ulErrorCode; + + /* Read back the data written.*/ + ReadParams.ulReadAddress = WriteParams.ulWriteAddress; + ReadParams.pusReadData = &usReadData; + mOCT6100_DRIVER_READ_API( ReadParams, ulResult ) + if ( ulResult != cOCT6100_ERR_OK ) + return ulResult; - if ( usReadData != (UINT16)(0x1 << (i / 2)) ) - return f_ulErrorCode; + if ( usReadData != (UINT16)(0x1 << i) ) + return f_ulErrorCode; + } } /* Perform the first write at address 0 + mem base */ @@ -5394,6 +5996,7 @@ UINT32 Oct6100ApiRandomMemoryWrite( return f_ulErrorCode; } + return cOCT6100_ERR_OK; } #endif @@ -5895,7 +6498,6 @@ UINT32 Oct6100FreeResourcesSer( return ulResult; } } - /* Close all TSI connections. */ if ( f_pFreeResources->fFreeTsiConnections == TRUE ) { @@ -5919,7 +6521,6 @@ UINT32 Oct6100FreeResourcesSer( } } } - /* Close all conference bridges. */ if ( f_pFreeResources->fFreeConferenceBridges == TRUE ) { @@ -5969,7 +6570,6 @@ UINT32 Oct6100FreeResourcesSer( } } - /* Close all phasing TSSTs. */ if ( f_pFreeResources->fFreePhasingTssts == TRUE ) { @@ -5992,7 +6592,6 @@ UINT32 Oct6100FreeResourcesSer( } } } - /* Close all ADPCM channels. */ if ( f_pFreeResources->fFreeAdpcmChannels == TRUE ) { @@ -6015,7 +6614,6 @@ UINT32 Oct6100FreeResourcesSer( } } - return cOCT6100_ERR_OK; } #endif |