From 9e4d29ff9c697b831782229bc26a53ee6ef9a7d5 Mon Sep 17 00:00:00 2001 From: markster Date: Tue, 11 Dec 2001 21:12:45 +0000 Subject: Version 0.1.4 from FTP git-svn-id: http://svn.digium.com/svn/zaptel/trunk@41 5390a7c7-147a-4af0-8ec9-7488f05a26cb --- tormenta2.vhd | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 58 insertions(+), 10 deletions(-) (limited to 'tormenta2.vhd') diff --git a/tormenta2.vhd b/tormenta2.vhd index 19b23bb..65c3949 100755 --- a/tormenta2.vhd +++ b/tormenta2.vhd @@ -1,5 +1,5 @@ -- Tormenta2 -- PCI Telephony Interface Card -- VHDL for Xilinx Part --- version 1.1, 10/22/2001. +-- version 1.3, 12/11/2001. -- Copyright (c) 2001, Jim Dixon. -- -- Jim Dixon @@ -160,6 +160,10 @@ signal clkreg: std_logic_vector(2 downto 0); signal ctlreg: std_logic_vector(7 downto 0); -- Status register signal statreg: std_logic_vector(2 downto 0); +-- LED register +signal ledreg: std_logic_vector(7 downto 0); +-- LED cycle counter +signal ledcnt: std_logic_vector(1 downto 0); -- Signal actually driving Rx buffers (after Rxserial loopback mux) signal xrser: std_logic; -- Signal actually driven by Tx buffers (before Txserial loopback mux) @@ -174,6 +178,7 @@ signal xtser: std_logic; -- bit 1 - Drives "TEST1" signal ("Interrupt" outbit) -- bit 2 - Dallas Interrupt Enable (Allows DINT signal to drive INT) -- bit 3 - Enable External Synronization Drive (MASTER signal). +-- bit 4 - Select E1 Divisor Mode (0 for T1, 1 for E1) -- bit 5 - Remote serial loopback (When set to 1, TSER is driven from RSER) -- bit 6 - Local serial loopback (When set to 1, Rx buffers are driven from Tx buffers) -- bit 7 - Interrupt Acknowledge (set to 1 to acknowledge interrupt) @@ -354,17 +359,21 @@ begin ); -clkdiv193: process(lclk) -- Divider from 1.544 Mhz to 8 Khz to drive MK1574 via KHZ8000 pin +clkdiv193: process(lclk,ctlreg(4)) -- Divider from 1.544 Mhz (or 2.048 MHZ for E1) to 8 Khz to drive MK1574 via KHZ8000 pin begin if (lclk'event and lclk = '1') then cnt193 <= cnt193 + 1; - -- Go high after 96 samples and - -- low after 193 samples - if (cnt193 = "01100000") then - KHZ8000 <= '1'; - elsif (cnt193 = "11000000") then -- *YES* C0 hex *IS* the correct value. I even checked it on a freq. counter! - KHZ8000 <= '0'; - cnt193 <= "00000000"; + if (ctlreg(4) = '0') then -- For T1 operation + -- Go high after 96 samples and + -- low after 193 samples + if (cnt193 = "01100000") then + KHZ8000 <= '1'; + elsif (cnt193 = "11000000") then -- *YES* C0 hex *IS* the correct value. I even checked it on a freq. counter! + KHZ8000 <= '0'; + cnt193 <= "00000000"; + end if; + else -- For E1 operation, it naturally divides by 256 (being an 8 bit counter) + KHZ8000 <= cnt193(7); end if; end if; end process clkdiv193; @@ -415,6 +424,45 @@ begin elsif (ctlreg(7)='1' or ctlreg(0)='0') then statreg(1) <= '0'; -- If interrupt ack-ed end if; + -- If we are on an 16 sample boundary, twiddle LED's + if (lcounter="00000000000000") then + -- We make this 3 count sequence, because we need 2/3 green and 1/3 red to make + -- yellow. Half and half makes sorta orange (yuch!). Bit 1 of the ledcnt will + -- be 0 for 2 counts, then 1 for 1 count. Perfict for making yellow! + if (ledcnt="10") then + ledcnt <= "00"; -- 3 count sequence + else + ledcnt <= ledcnt + 1; + end if; + -- Logic for LED 1 + if (ledreg(1 downto 0)="11") then -- If yellow, use count seq. + LEDS(0) <= ledcnt(1); + LEDS(1) <= not ledcnt(1); + else -- Otherwise is static + LEDS(1 downto 0) <= not ledreg(1 downto 0); + end if; + -- Logic for LED 2 + if (ledreg(3 downto 2)="11") then -- If yellow, use count seq. + LEDS(2) <= ledcnt(1); + LEDS(3) <= not ledcnt(1); + else -- Otherwise is static + LEDS(3 downto 2) <= not ledreg(3 downto 2); + end if; + -- Logic for LED 3 + if (ledreg(5 downto 4)="11") then -- If yellow, use count seq. + LEDS(4) <= ledcnt(1); + LEDS(5) <= not ledcnt(1); + else -- Otherwise is static + LEDS(5 downto 4) <= not ledreg(5 downto 4); + end if; + -- Logic for LED 4 + if (ledreg(7 downto 6)="11") then -- If yellow, use count seq. + LEDS(6) <= ledcnt(1); + LEDS(7) <= not ledcnt(1); + else -- Otherwise is static + LEDS(7 downto 6) <= not ledreg(7 downto 6); + end if; + end if; end if; end process; @@ -516,7 +564,7 @@ if (CLK'event and CLK='1') then -- On positive transition of clock if (BE(1 downto 0)="11") then TEST2 <= D(0); -- Write to TEST2 pin (0xC03) elsif (BE(1 downto 0)="10") then - LEDS <= not D(7 downto 0); -- Write to the LED register (0xC02) + ledreg <= D(7 downto 0); -- Write to the LED register (0xC02) elsif (BE(1 downto 0)="01") then ctlreg <= D(7 downto 0); -- Write to the ctlreg register (0xC01) else -- cgit v1.2.3