Version 0.3.2 from FTP

git-svn-id: http://svn.digium.com/svn/zaptel/trunk@116 5390a7c7-147a-4af0-8ec9-7488f05a26cb

1 files changed, 47 insertions, 26 deletions

diff --git a/tormenta2.vhd b/tormenta2.vhd
index 65c3949..d82da29 100755
--- a/tormenta2.vhd
+++ b/tormenta2.vhd
@@ -1,6 +1,6 @@
 -- Tormenta2 -- PCI Telephony Interface Card -- VHDL for Xilinx Part
--- version 1.3, 12/11/2001.
--- Copyright (c) 2001, Jim Dixon. 
+-- version 1.4, 10/10/2002.
+-- Copyright (c) 2001-2002, Jim Dixon. 
 --
 -- Jim Dixon <jim@lambdatel.com>
 -- Mark Spencer <mark@linux-support.net>
@@ -156,8 +156,10 @@ signal lclk: std_logic;
 signal cnt193: std_logic_vector(7 downto 0);
 -- Which of the received clocks to propagate
 signal clkreg: std_logic_vector(2 downto 0);
--- Control register
+-- First Control register
 signal ctlreg: std_logic_vector(7 downto 0);
+-- Second Control register
+signal ctlreg1: std_logic_vector(7 downto 0);
 -- Status register
 signal statreg: std_logic_vector(2 downto 0);
 -- LED register
@@ -168,41 +170,44 @@ signal ledcnt: std_logic_vector(1 downto 0);
 signal xrser: std_logic;
 -- Signal actually driven by Tx buffers (before Txserial loopback mux)
 signal xtser: std_logic;
+signal tssync_local: std_logic;
+signal rsync_reva: std_logic;
 
 -- Register definitions:
 
 -- Write:
 -- 0xC00 -- clkreg (sync source) 0=free run, 1=span 1, 2=span 2, 3=span 3, 4=span 4, 5=external.
 -- 0xC01 -- ctlreg as follows:
---		bit 0 - Interrupt Enable
---    bit 1 - Drives "TEST1" signal ("Interrupt" outbit)
---	   bit 2 - Dallas Interrupt Enable (Allows DINT signal to drive INT)
---		bit 3 - Enable External Synronization Drive (MASTER signal).
---		bit 4 - Select E1 Divisor Mode (0 for T1, 1 for E1)
---    bit 5 - Remote serial loopback (When set to 1, TSER is driven from RSER)
---		bit 6 - Local serial loopback (When set to 1, Rx buffers are driven from Tx buffers)
---    bit 7 - Interrupt Acknowledge (set to 1 to acknowledge interrupt)
+--	bit 0 - Interrupt Enable
+--   bit 1 - Drives "TEST1" signal ("Interrupt" outbit)
+--	bit 2 - Dallas Interrupt Enable (Allows DINT signal to drive INT)
+--	bit 3 - Enable External Synronization Drive (MASTER signal).
+--	bit 4 - Select E1 Divisor Mode (0 for T1, 1 for E1)
+--   bit 5 - Remote serial loopback (When set to 1, TSER is driven from RSER)
+--	bit 6 - Local serial loopback (When set to 1, Rx buffers are driven from Tx buffers)
+--   bit 7 - Interrupt Acknowledge (set to 1 to acknowledge interrupt)
 -- 0xC02 -- LED register as follows:
---		bit 0 - Span 1 Green
+--	bit 0 - Span 1 Green
 -- 	bit 1 - Span 1 Red
---		bit 2 - Span 2 Green
---		bit 3 - Span 2 Red
---		bit 4 - Span 3 Green
---		bit 5 - Span 3 Red
+--	bit 2 - Span 2 Green
+--	bit 3 - Span 2 Red
+--	bit 4 - Span 3 Green
+--	bit 5 - Span 3 Red
 -- 	bit 6 - Span 4 Green
 -- 	bit 7 - Span 4 Red
---			NOTE: turning on both red and green yields yellow.
+--	NOTE: turning on both red and green yields yellow.
 -- 0xC03 -- TEST2, writing to bit 0 drives TEST2 pin.
+-- 0xC04 -- ctlreg1 as follows:
+--	bit 0 - Non-REV.A Timing mode (set for REV. B Dallas chip and higher)
 --
 -- Read:
 -- 0xC00 -- statreg as follows:
---		bit 0 - Interrupt Enabled
---		bit 1 - Interrupt Active
+--	bit 0 - Interrupt Enabled
+--	bit 1 - Interrupt Active
 -- 	bit 2 - Dallas Chip Interrupt Active
 -- 0xC01 -- boardid as follows:
---    bits 0-3 Board ID bits 0-3 (from rotary dip switch)
-
-
+--   bits 0-3 Board ID bits 0-3 (from rotary dip switch)
+	
 begin
 
 	-- Create statreg for user to be able to read
@@ -414,9 +419,9 @@ begin
 		ldbuf <= dbuf;
 		lposition <= position;
 		if (lcounter(9 downto 0)="0000000000") then -- Generate TSSYNC signal
-			TSSYNC <= '1'; 
+			TSSYNC_LOCAL <= '1'; 
 		else
-			TSSYNC <= '0';
+			TSSYNC_LOCAL <= '0';
 		end if;
 		-- If we are on an 8 sample boundary, and interrupts are enabled, 
 		if (((lcounter(12 downto 0)="0000000000000") and (ctlreg(0)='1'))) then
@@ -472,9 +477,9 @@ begin
 if (CLK8192'event and CLK8192='0') then
 	lcounter <= counter;  -- save local copy of counter
 	if (counter(9 downto 0)="0000000000") then
-		RSYNC <= '1';  -- Generate RSYNC pulse
+		RSYNC_REVA <= '1';  -- Generate RSYNC pulse
 	else
-		RSYNC <= '0';
+		RSYNC_REVA <= '0';
 	end if;
 end if;
 end process;
@@ -571,6 +576,11 @@ if (CLK'event and CLK='1') then -- On positive transition of clock
 				clkreg <= D(2 downto 0); -- Write to the clkreg register (0xC00)
 			end if;
 		end if;
+		if (ADDR(7 downto 2)="000001") then
+			if (BE(1 downto 0)="00") then
+				ctlreg1 <= D(7 downto 0); -- Write to the ctlreg1 register (0xC04)
+			end if;
+		end if;
 	end if;
 	if ((statreg(1)='0') and (ctlreg(7)='1')) then -- if interrupt acked and de-asserted, ack the ack 
 		ctlreg(7) <= '0';
@@ -633,4 +643,15 @@ if ((WR='0' or RD='0') and ADDR(11 downto 10)/="10") then  -- If during not vali
 end if;
 end process;
 
+-- MUX for Frame sync lines depending upon part revision
+process(tssync_local,rsync_reva,ctlreg1(0 downto 0))
+begin
+	if (ctlreg1(0 downto 0) = "0") then -- Do output for Rev. A part
+		TSSYNC <= TSSYNC_LOCAL;
+		RSYNC <= RSYNC_REVA;
+	else
+		TSSYNC <= TSSYNC_LOCAL;
+		RSYNC <= TSSYNC_LOCAL;
+	end if;
+end process;
 end behavioral;