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-- Prototype VHDL for Zapata Telephony PCI Radio Card, Rev. A ver 0.2 11/22/04
-- Author: Jim Dixon, WB6NIL <jim@lambdatel.com>
--
-- Copyright (c) 2001-2002, Jim Dixon.
--
-- Jim Dixon <jim@lambdatel.com>
--
-- This program is free software, and the design, schematics, layout,
-- and artwork for the hardware on which it runs is free, and all are
-- distributed under the terms of the GNU General Public License.
--
-- Implements the following registers:
--
-- Offset 0, Write
-- Bit 0 - SCLK
-- Bit 1 - DIN
-- Bit 4-7 CS0 thru CS3
--
-- Offset 1, Write
-- Bit 0-3 - PTT 0-3
-- Bit 4-7 - Test 0-3
--
-- Offset 2, Write
-- Bit 0-7 - LED's
--
-- Offset 0, Read
-- Bit 0-3 - COR 0-3
-- Bit 4 - DOUT
--
-- Offset 1, Read
-- Bit 0-3 - UIOA0-3
-- Bit 4-7 - UIOB0-3
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pciradio is
Port ( CLK0 : in std_logic;
RST : in std_logic;
CLK : out std_logic;
FS : out std_logic_vector(3 downto 0);
WRITE : in std_logic;
READ : in std_logic;
A : in std_logic_vector(3 downto 0);
D : inout std_logic_vector(7 downto 0);
LED : out std_logic_vector(7 downto 0);
COR : in std_logic_vector(3 downto 0);
PTT : out std_logic_vector(3 downto 0);
TEST : out std_logic_vector(3 downto 0);
UIOA : in std_logic_vector(3 downto 0);
UIOB : in std_logic_vector(3 downto 0);
CS : out std_logic_vector(3 downto 0);
SCLK : out std_logic;
DIN : out std_logic;
DOUT : in std_logic;
IRQ : in std_logic;
TJFSC : out std_logic );
end pciradio;
architecture Behavioral of pciradio is
component IBUFG
port
(
I : in std_logic;
O : out std_logic
);
end component;
signal counter: std_logic_vector(8 downto 0);
signal WR,RD : std_logic;
signal DBW,DBR : std_logic_vector(7 downto 0);
begin
ibufg_rd : IBUFG
port map
(
I => READ,
O => RD
);
ibufg_wr : IBUFG
port map
(
I => WRITE,
O => WR
);
CLK <= not counter(0);
doclk: process(CLK0)
begin
if CLK0'event and CLK0='0' then
counter <= counter + 1;
end if;
end process;
makefs: process(counter)
begin
TJFSC <= '0';
if (counter = "00000000") then
TJFSC <= '1';
elsif (counter = "111111110") then
FS <= "0001";
elsif (counter = "000001110")then
FS <= "0010";
elsif (counter = "000011110") then
FS <= "0100";
elsif (counter = "000101110") then
FS <= "1000";
else FS <= "0000";
end if;
end process;
iowrite: process(A,WR)
begin
if(RST = '0') then
TEST <= "0000";
PTT <= "1111";
LED <= "00000000";
CS <= "1111";
DIN <= '0';
SCLK <= '0';
elsif(WR'event) and (WR = '1') then
if(A = "0001") then
TEST <= DBW(7 downto 4);
PTT <= not DBW(3 downto 0);
elsif(A = "0010") then
LED <= DBW;
elsif(A = "0000") then
SCLK <= DBW(0);
DIN <= DBW(1);
CS <= DBW(7 downto 4);
end if;
end if;
end process iowrite;
rdmux : process(A)
begin
if(A = "0000") then
DBR(3 downto 0) <= COR;
DBR(4) <= DOUT;
DBR(5) <= IRQ;
DBR(7 downto 6) <= "00";
elsif(A = "0001") then
DBR(3 downto 0) <= UIOA;
DBR(7 downto 4) <= UIOB;
else
DBR <= "00000000";
end if;
end process rdmux;
D <= DBR when RD = '0' else "ZZZZZZZZ";
DBW <= D;
end Behavioral;
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