Center T1 channels on TDM bus when running fully T12 mode

git-svn-id: http://svn.digium.com/svn/zaptel/trunk@435 5390a7c7-147a-4af0-8ec9-7488f05a26cb

1 files changed, 19 insertions, 6 deletions

diff --git a/wct4xxp.c b/wct4xxp.c
index b1c309a..57caca3 100755
--- a/wct4xxp.c
+++ b/wct4xxp.c
@@ -620,10 +620,17 @@ static void t4_serial_setup(struct t4 *wc, int unit)
 	t4_framer_out(wc, unit, 0x3f, unit << 1); /* SIC2: No FFS, no center receive eliastic buffer, phase */
 	t4_framer_out(wc, unit, 0x40, 0x04);	/* SIC3: Edges for capture */
 	t4_framer_out(wc, unit, 0x45, 0x00);	/* CMR2: We provide sync and clock for tx and rx. */
-	t4_framer_out(wc, unit, 0x22, 0x00);	/* XC0: Normal operation of Sa-bits */
-	t4_framer_out(wc, unit, 0x23, 0x04);	/* XC1: 0 offset */
-	t4_framer_out(wc, unit, 0x24, 0x04);	/* RC0: Just shy of 1023 */
-	t4_framer_out(wc, unit, 0x25, 0x04);	/* RC1: The rest of RC0 */
+	if (!wc->t1e1) {
+		t4_framer_out(wc, unit, 0x22, 0x03);	/* XC0: Normal operation of Sa-bits */
+		t4_framer_out(wc, unit, 0x23, 0x84);	/* XC1: 0 offset */
+		t4_framer_out(wc, unit, 0x24, 0x03);	/* RC0: Just shy of 1023 */
+		t4_framer_out(wc, unit, 0x25, 0x84);	/* RC1: The rest of RC0 */
+	} else {
+		t4_framer_out(wc, unit, 0x22, 0x00);	/* XC0: Normal operation of Sa-bits */
+		t4_framer_out(wc, unit, 0x23, 0x04);	/* XC1: 0 offset */
+		t4_framer_out(wc, unit, 0x24, 0x04);	/* RC0: Just shy of 1023 */
+		t4_framer_out(wc, unit, 0x25, 0x04);	/* RC1: The rest of RC0 */
+	}
 	
 	/* Configure ports */
 	t4_framer_out(wc, unit, 0x80, 0x00);	/* PC1: SPYR/SPYX input on RPA/XPA */
@@ -909,6 +916,9 @@ static void t4_receiveprep(struct t4 *wc, int irq)
 	int dbl = 0;
 	int x,y,z;
 	unsigned int tmp;
+	int offset;
+	if (!wc->t1e1)
+		offset = 4;
 	if (irq & 1) {
 		/* First part */
 		readchunk = wc->readchunk;
@@ -930,7 +940,7 @@ static void t4_receiveprep(struct t4 *wc, int irq)
 	for (x=0;x<ZT_CHUNKSIZE;x++) {
 		for (z=0;z<24;z++) {
 			/* All T1/E1 channels */
-			tmp = readchunk[z+1];
+			tmp = readchunk[z+1+offset];
 			wc->spans[3].chans[z].readchunk[x] = tmp & 0xff;
 			wc->spans[2].chans[z].readchunk[x] = (tmp & 0xff00) >> 8;
 			wc->spans[1].chans[z].readchunk[x] = (tmp & 0xff0000) >> 16;
@@ -983,6 +993,9 @@ static void t4_transmitprep(struct t4 *wc, int irq)
 	volatile unsigned int *writechunk;
 	int x,y,z;
 	unsigned int tmp;
+	int offset;
+	if (!wc->t1e1)
+		offset = 4;
 	if (irq & 1) {
 		/* First part */
 		writechunk = wc->writechunk + 1;
@@ -1002,7 +1015,7 @@ static void t4_transmitprep(struct t4 *wc, int irq)
 				  (wc->spans[2].chans[z].writechunk[x] << 8) |
 				  (wc->spans[1].chans[z].writechunk[x] << 16) |
 				  (wc->spans[0].chans[z].writechunk[x] << 24);
-			writechunk[z] = tmp;
+			writechunk[z+offset] = tmp;
 		}
 		if (wc->t1e1) {
 			for (z=24;z<31;z++) {