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authortzafrir <tzafrir@5390a7c7-147a-4af0-8ec9-7488f05a26cb>2007-05-17 22:55:21 +0000
committertzafrir <tzafrir@5390a7c7-147a-4af0-8ec9-7488f05a26cb>2007-05-17 22:55:21 +0000
commit3af1b5fa2ec86d21762ad1cea81d2b275d4a9d48 (patch)
tree12da5f31396b3b1d3f99ed1bad8725bd50120689 /xpp/init_card_6_26
parentc16f6ead0e9050d59d73f39f3015ecb64aecc214 (diff)
XPP revision 3965:
* Tested with zaptel-1.2.17.1 * Add D-Channel TX, RX and BAD frames count in /proc/xpp/XBUS-*/XPD-*/bri_info * Adjust output of xpp_sync script. Pad for 8 port BRI. * Added a debugging module parport_debug (not compiled by default). * Added an optional patch to zaptel: - compiles only if ZAPTEL_SYNC_TICK is defined - Allow interested driver to register for "sync" notification. - Does not affect drivers that do not use this feature. * Added external synchronization feature: - Only if ZAPTEL_SYNC_TICK feature is compiled in - Than XPP may be synchronized by another card (e.g: an Astribank with FXS can be synchronized by a Digium PRI card). - May be enabled/disabled in runtime via the 'sync_tick_active' module parameter to the xpp.ko module. * Fixed a potential bug in D-Channel hexdump printing. * New visual indications in BRI leds: - Constant ON RED/GREEN: Shows the port type -- NT/TE. - Very fast "double blink": Layer1 work, no D-Channel yet. - Steady blinking (1/2 sec): D-Channel trafic detected. * xpp_fxloader moved to /usr/share/zaptel . * adj_clock removed: never really used. * Now we have Zaptel::Hardware and a sample zaptel_hardware script (not (installed by default). * We also have a sample perl zapconf (not installed by default) which aims at replacing genzaptelconf (sans the modules detection). git-svn-id: http://svn.digium.com/svn/zaptel/trunk@2537 5390a7c7-147a-4af0-8ec9-7488f05a26cb
Diffstat (limited to 'xpp/init_card_6_26')
-rwxr-xr-xxpp/init_card_6_269
1 files changed, 7 insertions, 2 deletions
diff --git a/xpp/init_card_6_26 b/xpp/init_card_6_26
index 2193a66..0da1f61 100755
--- a/xpp/init_card_6_26
+++ b/xpp/init_card_6_26
@@ -199,9 +199,14 @@ sub setup_fifo {
# my $fifonum = 0x80 | ($portnum << 3) | ($chan << 1) | ($direction); # # MSB first
my $fifonum = ($portnum << 3) | ($chan << 1) | ($direction); # # MSB first
my $r_slot = ($portnum << 3) | ($chan << 1) | ($direction);
- # receive data from STIO2, transmit to STIO1
+
+ # channel order workaround, swap odd and even portnums in $r_slot for PCM (chan 0, 1) only
+ if ("$chan" == 0 || "$chan" == 1) {
+ $r_slot = $r_slot ^ 0x08;
+ }
+
my $short_portnum = $portnum & 0x03;
- my $a_sl_cfg = (0x80 | ($short_portnum << 3) | ($chan << 1) | ($direction));
+ my $a_sl_cfg = (0x80 | ($short_portnum << 3) | ($chan << 1) | ($direction)); # receive data from STIO2, transmit to STIO1
#logit "setup_fifo($fifonum)";
xhfc_selfifo $fifonum;