diff options
| author | tzafrir <tzafrir@5390a7c7-147a-4af0-8ec9-7488f05a26cb> | 2006-09-09 11:37:10 +0000 |
|---|---|---|
| committer | tzafrir <tzafrir@5390a7c7-147a-4af0-8ec9-7488f05a26cb> | 2006-09-09 11:37:10 +0000 |
| commit | 90618eec2720e1c166cc96a03cae851d60f0cdc1 (patch) | |
| tree | 11439f3366bcba9e27bc90f61064021600c1573c /xpp | |
| parent | dd4b70e4f08d483d12ebaf74815579432b113be6 (diff) | |
Bugfix: Shorten max lines < MAX_PROC_WRITE
git-svn-id: http://svn.digium.com/svn/zaptel/trunk@1453 5390a7c7-147a-4af0-8ec9-7488f05a26cb
Diffstat (limited to 'xpp')
| -rw-r--r-- | xpp/init_data_3_19.cmd | 9 | ||||
| -rw-r--r-- | xpp/init_data_3_20.cmd | 9 | ||||
| -rw-r--r-- | xpp/init_data_4_19.cmd | 2 | ||||
| -rw-r--r-- | xpp/init_data_4_20.cmd | 2 |
4 files changed, 12 insertions, 10 deletions
diff --git a/xpp/init_data_3_19.cmd b/xpp/init_data_3_19.cmd index 69bdb80..3f57660 100644 --- a/xpp/init_data_3_19.cmd +++ b/xpp/init_data_3_19.cmd @@ -17,14 +17,15 @@ ; ; SLICS CMD Reg High Low -; ----------------------------------==== 8-channel FXS unit initialization ===----------------------------------------- +; -------------------------------------- 8-channel FXS unit initialization ; INTERNAL PS -; Change SLICs states to "Open state"s (Off,all transfers tristated to avoid data collision), Voltage sense +; Change SLICs states to "Open state"s (Off,all transfers tristated to avoid +; data collision), Voltage sense FF 00 00 00 WD 40 00 FF 00 00 00 WD 6C 01 -; ------------------------------------- Initialization of indirect registers ------------------------------------------ +; ------------------------------------- Initialization of indirect registers FF 00 00 00 WI 00 55 C2 FF 00 00 00 WI 01 51 E6 @@ -88,7 +89,7 @@ FF 00 00 00 WI 66 79 C0 FF 00 00 00 WI 67 11 20 FF 00 00 00 WI 68 3B E0 -; ------------------------------------- Initialization of direct registers -------------------------------------------- +; ------------------------------------- Initialization of direct registers ; Mode(8-bit,u-Law,1 PCLK ) setting, Loopbacks and Interrupts clear diff --git a/xpp/init_data_3_20.cmd b/xpp/init_data_3_20.cmd index 5470357..01d801d 100644 --- a/xpp/init_data_3_20.cmd +++ b/xpp/init_data_3_20.cmd @@ -17,14 +17,15 @@ ; ; SLICS CMD Reg High Low -; ----------------------------------==== 8-channel FXS unit initialization ===----------------------------------------- +; -------------------------------------- 8-channel FXS unit initialization ; INTERNAL PS -; Change SLICs states to "Open state"s (Off,all transfers tristated to avoid data collision), Voltage sense +; Change SLICs states to "Open state"s (Off,all transfers tristated to avoid +; data collision), Voltage sense FF 00 00 00 WD 40 00 FF 00 00 00 WD 6C 01 -; ------------------------------------- Initialization of indirect registers ------------------------------------------ +; ------------------------------------- Initialization of indirect registers FF 00 00 00 WI 00 55 C2 FF 00 00 00 WI 01 51 E6 @@ -88,7 +89,7 @@ FF 00 00 00 WI 66 79 C0 FF 00 00 00 WI 67 11 20 FF 00 00 00 WI 68 3B E0 -; ------------------------------------- Initialization of direct registers -------------------------------------------- +; ------------------------------------- Initialization of direct registers ; Mode(8-bit,u-Law,1 PCLK ) setting, Loopbacks and Interrupts clear diff --git a/xpp/init_data_4_19.cmd b/xpp/init_data_4_19.cmd index 3223fb7..ba439a3 100644 --- a/xpp/init_data_4_19.cmd +++ b/xpp/init_data_4_19.cmd @@ -17,7 +17,7 @@ ; ; DAA's CMD Reg High Low -; ----------------------------------==== 8-channel FXO unit initialization ===----------------------------------------- +; -------------------------------------- 8-channel FXO unit initialization FF FF 00 00 WD 21 28 FF FF 00 00 WD 18 99 diff --git a/xpp/init_data_4_20.cmd b/xpp/init_data_4_20.cmd index 10533f1..3f809c2 100644 --- a/xpp/init_data_4_20.cmd +++ b/xpp/init_data_4_20.cmd @@ -20,7 +20,7 @@ ; Start with a software reset: FF FF 00 00 WD 01 80 -; ----------------------------------==== 8-channel FXO unit initialization ===----------------------------------------- +; -------------------------------------- 8-channel FXO unit initialization FF FF 00 00 WD 21 28 ; 99 also sets ring validation |