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-rw-r--r--wcfxo.c75
1 files changed, 50 insertions, 25 deletions
diff --git a/wcfxo.c b/wcfxo.c
index fd0772d..5f48051 100644
--- a/wcfxo.c
+++ b/wcfxo.c
@@ -74,6 +74,27 @@
#define WC_SERCTL 0x2d
#define WC_FSCDELAY 0x2f
+
+/* DAA registers */
+#define WC_DAA_CTL1 1
+#define WC_DAA_CTL2 2
+#define WC_DAA_DCTL1 5
+#define WC_DAA_DCTL2 6
+#define WC_DAA_PLL1_N1 7
+#define WC_DAA_PLL1_M1 8
+#define WC_DAA_PLL2_N2_M2 9
+#define WC_DAA_PLL_CTL 10
+#define WC_DAA_CHIPA_REV 11
+#define WC_DAA_LINE_STAT 12
+#define WC_DAA_CHIPB_REV 13
+#define WC_DAA_DAISY_CTL 14
+#define WC_DAA_TXRX_GCTL 15
+#define WC_DAA_INT_CTL1 16
+#define WC_DAA_INT_CTL2 17
+#define WC_DAA_INT_CTL3 18
+#define WC_DAA_INT_CTL4 19
+
+
#define FLAG_EMPTY 0
#define FLAG_WRITE 1
#define FLAG_READ 2
@@ -113,7 +134,10 @@ struct reg {
};
static int wecareregs[] =
-{ 5, 6, 9, 11, 12, 13, 17, 19, };
+{
+ WC_DAA_DCTL1, WC_DAA_DCTL2, WC_DAA_PLL2_N2_M2, WC_DAA_CHIPA_REV,
+ WC_DAA_LINE_STAT, WC_DAA_CHIPB_REV, WC_DAA_INT_CTL2, WC_DAA_INT_CTL4,
+};
struct wcfxo {
struct pci_dev *dev;
@@ -327,9 +351,9 @@ static inline void wcfxo_receiveprep(struct wcfxo *wc, unsigned char ints)
realreg = wecareregs[(wc->regs[x].index + wc->regoffset) %
(sizeof(wecareregs) / sizeof(wecareregs[0]))];
realval = (le32_to_cpu(readchunk[(x << 1) +wc->alt]) >> 16) & 0xff;
- if ((realval == 0x89) && (realreg != 0x9)) {
+ if ((realval == 0x89) && (realreg != WC_DAA_PLL2_N2_M2)) {
/* Some sort of slippage, correct for it */
- while(realreg != 0x9) {
+ while(realreg != WC_DAA_PLL2_N2_M2) {
/* Find register 9 */
realreg = wecareregs[(wc->regs[x].index + ++wc->regoffset) %
(sizeof(wecareregs) / sizeof(wecareregs[0]))];
@@ -468,7 +492,7 @@ ZAP_IRQ_HANDLER(wcfxo_interrupt)
}
if (1 /* !(wc->report % 0xf) */) {
/* Check for BATTERY from register and debounce for 8 ms */
- b = wc->readregs[0xc] & 0xf;
+ b = wc->readregs[WC_DAA_LINE_STAT] & 0xf;
if (!b) {
wc->nobatttimer++;
#if 0
@@ -496,7 +520,7 @@ ZAP_IRQ_HANDLER(wcfxo_interrupt)
wc->battdebounce = BATT_DEBOUNCE;
if ((wc->nobatttimer > 5000) &&
#ifdef ZERO_BATT_RING
- !(wc->readregs[0x05] & 0x04) &&
+ !(wc->readregs[WC_DAA_DCTL1] & 0x04) &&
#endif
(!wc->span.alarms)) {
wc->span.alarms = ZT_ALARM_RED;
@@ -599,11 +623,11 @@ static int wcfxo_hooksig(struct zt_chan *chan, zt_txsig_t txsig)
case ZT_TXSIG_OFFHOOK:
/* Take off hook and enable normal mode reception. This must
be done in two steps because of a hardware bug. */
- reg = wc->readregs[0x5] & ~0x08;
- wcfxo_setreg(wc, 0x5, reg);
+ reg = wc->readregs[WC_DAA_DCTL1] & ~0x08;
+ wcfxo_setreg(wc, WC_DAA_DCTL1, reg);
reg = reg | 0x1;
- wcfxo_setreg(wc, 0x5, reg);
+ wcfxo_setreg(wc, WC_DAA_DCTL1, reg);
wc->offhook = 1;
#ifdef JAPAN
wc->battery = 1;
@@ -613,11 +637,11 @@ static int wcfxo_hooksig(struct zt_chan *chan, zt_txsig_t txsig)
break;
case ZT_TXSIG_ONHOOK:
/* Put on hook and enable on hook line monitor */
- reg = wc->readregs[0x5] & 0xfe;
- wcfxo_setreg(wc, 0x5, reg);
+ reg = wc->readregs[WC_DAA_DCTL1] & 0xfe;
+ wcfxo_setreg(wc, WC_DAA_DCTL1, reg);
reg = reg | 0x08;
- wcfxo_setreg(wc, 0x5, reg);
+ wcfxo_setreg(wc, WC_DAA_DCTL1, reg);
wc->offhook = 0;
/* Don't accept a ring for another 1000 ms */
wc->ringdebounce = 1000;
@@ -777,9 +801,9 @@ static void wcfxo_set_daa_mode(struct wcfxo *wc)
return;
}
- wcfxo_setreg(wc, 16, reg16);
- wcfxo_setreg(wc, 17, reg17);
- wcfxo_setreg(wc, 18, reg18);
+ wcfxo_setreg(wc, WC_DAA_INT_CTL1, reg16);
+ wcfxo_setreg(wc, WC_DAA_INT_CTL2, reg17);
+ wcfxo_setreg(wc, WC_DAA_INT_CTL3, reg18);
/* Wait a couple of jiffies for our writes to finish */
@@ -799,17 +823,17 @@ static int wcfxo_init_daa(struct wcfxo *wc)
// schedule_timeout(10);
/* Soft-reset it */
- wcfxo_setreg(wc, 0x1, 0x80);
+ wcfxo_setreg(wc, WC_DAA_CTL1, 0x80);
/* Let the reset go */
set_current_state(TASK_UNINTERRUPTIBLE);
schedule_timeout(1 + (ZT_CHUNKSIZE * HZ) / 800);
/* We have a clock at 18.432 Mhz, so N1=1, M1=2, CGM=0 */
- wcfxo_setreg(wc, 0x7, 0x0); /* This value is N1 - 1 */
- wcfxo_setreg(wc, 0x8, 0x1); /* This value is M1 - 1 */
+ wcfxo_setreg(wc, WC_DAA_PLL1_N1, 0x0); /* This value is N1 - 1 */
+ wcfxo_setreg(wc, WC_DAA_PLL1_M1, 0x1); /* This value is M1 - 1 */
/* We want to sample at 8khz, so N2 = 9, M2 = 10 (N2-1, M2-1) */
- wcfxo_setreg(wc, 0x9, 0x89);
+ wcfxo_setreg(wc, WC_DAA_PLL2_N2_M2, 0x89);
/* Wait until the PLL's are locked. Time is between 100 uSec and 1 mSec */
set_current_state(TASK_INTERRUPTIBLE);
@@ -817,15 +841,15 @@ static int wcfxo_init_daa(struct wcfxo *wc)
/* No additional ration is applied to the PLL and faster lock times
* are possible */
- wcfxo_setreg(wc, 0xa, 0x0);
+ wcfxo_setreg(wc, WC_DAA_PLL_CTL, 0x0);
/* Enable off hook pin */
- wcfxo_setreg(wc, 0x5, 0x0a);
+ wcfxo_setreg(wc, WC_DAA_DCTL1, 0x0a);
if (monitor) {
/* Enable ISOcap and external speaker and charge pump if present */
- wcfxo_setreg(wc, 0x6, 0x80);
+ wcfxo_setreg(wc, WC_DAA_DCTL2, 0x80);
} else {
/* Enable ISOcap and charge pump if present (leave speaker disabled) */
- wcfxo_setreg(wc, 0x6, 0xe0);
+ wcfxo_setreg(wc, WC_DAA_DCTL2, 0xe0);
}
/* Wait a couple of jiffies for our writes to finish */
@@ -841,9 +865,10 @@ static int wcfxo_init_daa(struct wcfxo *wc)
printk("wcfxo: Boosting receive signal\n");
reg15 |= (boost & 0x3);
}
- wcfxo_setreg(wc, 0xf, reg15);
+ wcfxo_setreg(wc, WC_DAA_TXRX_GCTL, reg15);
- chip_revb = (wc->readregs[13] >> 2) & 0xF; /* REVB: reg. 13, bits 5:2 */
+ /* REVB: reg. 13, bits 5:2 */
+ chip_revb = (wc->readregs[WC_DAA_CHIPB_REV] >> 2) & 0xF;
wcfxo_dbg(wc->span, "DAA chip REVB is %x\n", chip_revb);
switch(chip_revb) {
case 1: case 2: case 3:
@@ -859,7 +884,7 @@ static int wcfxo_init_daa(struct wcfxo *wc)
}
/* Didn't get it right. Register 9 is still garbage */
- if (wc->readregs[0x9] != 0x89)
+ if (wc->readregs[WC_DAA_PLL2_N2_M2] != 0x89)
return -1;
#if 0
{ int x;
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-03 06:04:12 +0000