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#
# Written by Oron Peled <oron@actcom.co.il>
# Copyright (C) 2006, Xorcom
#
# All rights reserved.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# See the file LICENSE in the top level of this tarball.
#
;
; $Id$
;
; SLICS CMD Reg High Low
; ----------------------------------==== 8-channel FXS unit initialization ===-----------------------------------------
; INTERNAL PS
; Change SLICs states to "Open state"s (Off,all transfers tristated to avoid data collision), Voltage sense
FF 00 00 00 WD 40 00
FF 00 00 00 WD 6C 01
; ------------------------------------- Initialization of indirect registers ------------------------------------------
FF 00 00 00 WI 00 55 C2
FF 00 00 00 WI 01 51 E6
FF 00 00 00 WI 02 4B 85
FF 00 00 00 WI 03 49 37
FF 00 00 00 WI 04 33 33
FF 00 00 00 WI 05 02 02
FF 00 00 00 WI 06 02 02
FF 00 00 00 WI 07 01 98
FF 00 00 00 WI 08 01 98
FF 00 00 00 WI 09 06 11
FF 00 00 00 WI 0A 02 02
FF 00 00 00 WI 0B 00 E5
FF 00 00 00 WI 0C 0A 1C
FF 00 00 00 WI 0D 7B 30
FF 00 00 00 WI 0E 00 63
FF 00 00 00 WI 0F 00 00
FF 00 00 00 WI 10 78 70
FF 00 00 00 WI 11 00 7D
FF 00 00 00 WI 12 00 00
FF 00 00 00 WI 13 00 00
FF 00 00 00 WI 14 7E F0
FF 00 00 00 WI 15 01 60
FF 00 00 00 WI 16 00 00
FF 00 00 00 WI 17 20 00
FF 00 00 00 WI 18 20 00
FF 00 00 00 WI 19 00 00
FF 00 00 00 WI 1A 40 00
FF 00 00 00 WI 1B 40 00
FF 00 00 00 WI 1C 18 00
FF 00 00 00 WI 1D 40 00
FF 00 00 00 WI 1E 10 00
FF 00 00 00 WI 1F 00 80
FF 00 00 00 WI 20 0F F4
FF 00 00 00 WI 21 6E 7E
FF 00 00 00 WI 22 0F F4
FF 00 00 00 WI 23 88 00
FF 00 00 00 WI 24 03 20
FF 00 00 00 WI 25 00 12
FF 00 00 00 WI 26 00 12
FF 00 00 00 WI 27 00 12
FF 00 00 00 WI 28 0C 00
FF 00 00 00 WI 29 0C 00
FF 00 00 00 WI 2B 08 00
FF 00 00 00 WI 63 00 DA
FF 00 00 00 WI 64 6B 60
FF 00 00 00 WI 65 00 74
FF 00 00 00 WI 66 79 C0
FF 00 00 00 WI 67 11 20
FF 00 00 00 WI 68 3B E0
; ------------------------------------- Initialization of direct registers --------------------------------------------
; Mode(8-bit,u-Law,1 PCLK ) setting, Loopbacks and Interrupts clear
FF 00 00 00 WD 01 29
FF 00 00 00 WD 08 00
FF 00 00 00 WD 09 00
FF 00 00 00 WD 0E 00
FF 00 00 00 WD 15 00
FF 00 00 00 WD 16 03
FF 00 00 00 WD 17 00
FF 00 00 00 WD 12 FF
FF 00 00 00 WD 13 FF
FF 00 00 00 WD 14 FF
; Automatic/Manual Control: defaults - Cancel Power Alarm
FF 00 00 00 WD 43 1E
FF 00 00 00 WD 4A 31
FF 00 00 00 WD 4B 10
; Battery Feed Control: Battery low (DCSW low)
FF 00 00 00 WD 42 00
; Slic Calibration
FF 00 00 00 WD 61 1F
FF 00 00 00 WD 60 5F
; Loop Closure Debounce Interval
FF 00 00 00 WD 45 0A
; Ring Detect Debounce Interval
FF 00 00 00 WD 46 0B
; Loop Current Limit
FF 00 00 00 WD 47 07
; Setting of SLICs offsets
# New card initialization
01 00 00 00 WD 02 00
01 00 00 00 WD 03 00
01 00 00 00 WD 04 00
01 00 00 00 WD 05 00
02 00 00 00 WD 02 08
02 00 00 00 WD 03 00
02 00 00 00 WD 04 08
02 00 00 00 WD 05 00
04 00 00 00 WD 02 10
04 00 00 00 WD 03 00
04 00 00 00 WD 04 10
04 00 00 00 WD 05 00
08 00 00 00 WD 02 18
08 00 00 00 WD 03 00
08 00 00 00 WD 04 18
08 00 00 00 WD 05 00
10 00 00 00 WD 02 20
10 00 00 00 WD 03 00
10 00 00 00 WD 04 20
10 00 00 00 WD 05 00
20 00 00 00 WD 02 28
20 00 00 00 WD 03 00
20 00 00 00 WD 04 28
20 00 00 00 WD 05 00
40 00 00 00 WD 02 30
40 00 00 00 WD 03 00
40 00 00 00 WD 04 30
40 00 00 00 WD 05 00
80 00 00 00 WD 02 38
80 00 00 00 WD 03 00
80 00 00 00 WD 04 38
80 00 00 00 WD 05 00
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